TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch
data sheet (DS03-117HSPL-1).
TSWC02622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch
data sheet (DS03-118HSPL-1).
TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch
data sheet (DS03-120HSPL).
TSYN01622 SONET/SDH/PDH/ATM Clock Synthesizer
data sheet (DS03-119HSPL).
TSYN03622 SONET/SDH/PDH/ATM Clock Synthesizer
data sheet (DS03-130HSPL-1).
Note:
Customers must check with their Agere representative for the current version of this advisory; this is a continuously
updated document.
1 TSWC01622 October 2002, Device Exceptions
1.1 Exception 1—Squelch Mode
Applies to TSWC01622, TSWC02622, TSWC03622, TSYN01622, and TSYN03622.
Active 622.08 MHz and 155.52 MHz LVDS clocks are not affected by the squelch signal; therefore, they are active outputs
and not held in a low state when ENSQLN is enabled and all clocks (CLKA, CLKB, and CLKBU) have a fault.
The LVPECL and CMOS outputs (including the LVPECL and CMOS sync outputs) are compatible with the data sheet re-
garding squelch and enable signals. The LVDS sync outputs are also compatible with the data sheet.
Workaround:
No known workaround.
Corrective Action:
None.
1.2 Exception 2—Switching Out of Backup Clock Mode in Autonomous Nonrevertive Mode
Applies to TSWC01622, TSWC02622, and TSWC03622.
In autonomous, nonrevertive mode, if the TSWC01622 switches to the backup clock, it will not switch back to clock A or
clock B should either of the two input clocks become valid.
Workaround:
The device must be put into manual mode, and the appropriate input clock must be selected.
Corrective Action:
None.
TSWC01622/TSWC02622/TSWC03622/TSYN01622/TSYN03622
Device Version 1.1 Advisory
1.3 Exception 3—Backup Clock Input (CLKBU)
Applies to TSWC01622, TSWC02622, and TSWC03622.
Advisory
October 28, 2003
The TSWC01622 may not provide precise phase and frequency lock to CLKBU when the backup clock is configured for a
rate greater than 8 kHz. The TSWC01622 does provide precise phase and frequency lock when an 8 kHz backup clock rate
is selected and an 8 kHz clock is applied to CLKBU.
When the backup clock rate is configured for rates other than 8 kHz and the selected rate is applied to CLKBU, the output
clocks of the TSWC01622 may not be in phase alignment with CLKBU. However, the average frequency of the TSWC01622
output clocks will be proportional to the input frequency. For example, if an input clock rate of 38.88 MHz + 10 ppm is applied
to CLKBU, the TSWC01622 CMOS output CK19 will be at 19.44 MHz + 10 ppm.
Workaround:
Configure the TSWC01622 for a backup clock frequency of 8 kHz, and use a backup clock source of 8 kHz.
Corrective Action:
None.
1.4 Exception 4—Writing Registers Using the Serial Interface
Applies to TSWC01622, TSWC02622, TSWC03622, TSYN01622, and TSYN03622.
Occasionally, when executing a serial interface
write
operation, the
write
operation is not successful.
Workaround:
Two means can be applied as follows:
After performing a
write
operation, perform a
read
operation and examine the register contents to which the
write
operation
was intended. If the value contained in the register is incorrect, perform an additional
write
and
read
operation to verify reg-
ister contents.
Always perform two consecutive
write
operations to the same register without an intervening command. Two consecutive
write
operations have been verified to completely eliminate the occasional
write
operation error.
Corrective Action:
There is no additional corrective action deemed necessary for this issue as the work around completely
eliminates this issue.
2
Agere Systems Inc.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
docmaster@agere.com
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Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138
1-800-372-2447,
FAX 610-712-4106 (In CANADA:
1-800-553-2448,
FAX 610-712-4106)
ASIA:
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Tel. (852) 3129-2000,
FAX (852) 3129-2020
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(82) 2-767-1850
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(Taipei)
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Tel. (44) 1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Agere is a registered trademark of Agere Systems Inc. Agere Systems, the Agere logo,
1.1 Features ......................................................................................................................................................................1
4 Pin Information ...................................................................................................................................................................9
7.1 Input Clock Stability Requirements (Clock A and Clock B) ........................................................................................22
7.2 Input Frequency Selection (FINSEL[3:0]) ..................................................................................................................22
7.3 Input Electrical Level Selection for Clock A and Clock B Input Signals (SELLVDS) .................................................22
8.1 Available Output Clocks ............................................................................................................................................24
12 Output Specifications During Phase-Locked Condition (Nontransient Condition) ..........................................................35
12.1 Maximum Time Interval Error (MTIE) Specifications ...............................................................................................35
12.2 Time Deviation (TDEV) Specifications ....................................................................................................................36
13 Output Specifications During Transient Condition ..........................................................................................................37
13.1 Maximum Time Interval Error (MTIE) Specifications ...............................................................................................37
14 Other Input and PLL Specifications ................................................................................................................................38
14.1 Input Clock Maximum Rate of Phase Change During Transient .............................................................................38
15 Clock Switching State Machine and Software Interface .................................................................................................42
15.1 Clock Switching State Machine Behavior ................................................................................................................42
15.4 Loss of Clock Criteria ..............................................................................................................................................44
