INTEGRATED CIRCUITS
DATA SHEET
UDA1355H
Stereo audio codec with SPDIF
interface
Preliminary specification
2003 Apr 10
NXP Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
CONTENTS
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
8.1
8.2
8.3
8.4
9
9.1
9.2
9.3
10
10.1
10.2
10.3
10.4
FEATURES
General
Control
IEC 60958 input
IEC 60958 output
Digital I/O interface
ADC digital sound processing
DAC digital sound processing
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
IC control
Microcontroller interface
Clock systems
IEC 60958 decoder
IEC 60958 encoder
Analog input
Analog output
Digital audio input and output
Power-on reset
APPLICATION MODES
Static mode pin assignment
Static mode basic applications
Microcontroller mode pin assignment
Microcontroller mode applications
SPDIF SIGNAL FORMAT
SPDIF channel encoding
SPDIF hierarchical layers
Timing characteristics
L3-BUS DESCRIPTION
Device addressing
Register addressing
Data write mode
Data read mode
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
12
12.1
12.2
12.3
13
14
15
16
17
18
18.1
18.2
18.3
18.4
18.5
19
20
21
I
2
C-BUS DESCRIPTION
Characteristics
Bit transfer
Byte transfer
Data transfer
Register address
Device address
Start and stop conditions
Acknowledgment
Write cycle
Read cycle
REGISTER MAPPING
UDA1355H
Address mapping
Read/write registers mapping
Read registers mapping
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
TIMING CHARACTERISTICS
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DISCLAIMERS
TRADEMARKS
2003 Apr 10
2
NXP Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
1
1.1
FEATURES
General
UDA1355H
•
2.7 to 3.6 V power supply
•
Integrated digital interpolator filter and Digital-to-Analog
Converter (DAC)
•
24-bit data path in interpolator
•
No analog post filtering required for DAC
•
Integrated Analog-to-Digital Converter (ADC),
Programmable Gain Amplifier (PGA) and digital
decimator filter
•
24-bit data path in decimator
•
Master or slave mode for digital audio data I/O interface
•
I
2
S-bus, MSB-justified, LSB-justified 16, 18, 20,
and 24 bits formats supported on digital I/O interface.
1.2
Control
•
32, 44.1 and 48 kHz output frequencies (including
double and half of these frequencies) supported in
microcontroller mode
•
Via microcontroller, 40 status bits can be set for left and
right channel.
1.5
Digital I/O interface
•
Supports sampling frequencies from 16 to 100 kHz
•
Supported static mode:
– I
2
S-bus format
– LSB-justified 16 and 24 bits format
– MSB-justified format.
•
Supported microcontroller mode:
– I
2
S-bus format
– LSB-justified 16, 18, 20 or 24 bits format
– MSB-justified format.
•
BCK and WS signals can be slave or master, depending
on application mode.
1.6
ADC digital sound processing
•
Controlled by means of static pins or microcontroller
(L3-bus or I
2
C-bus) interface.
1.3
IEC 60958 input
•
On-chip amplifier for converting IEC 60958 input to
CMOS levels
•
Supports level I, II and III timing
•
Selectable IEC 60958 input channel, one of four
•
Supports input frequencies from 28 to 96 kHz
•
Lock indication signal available on pin LOCK
•
40 status bits can be read for left and right channel via
L3-bus or I
2
C-bus
•
Channel status bits available via L3-bus or I
2
C-bus: lock,
pre-emphasis, audio sample frequency, two channel
Pulse Code Modulation (PCM) indication and clock
accuracy
•
Pre-emphasis information of incoming IEC 60958
bitstream available in register
•
Detection of digital data preamble, such as AC3,
available on pin in microcontroller mode.
1.4
IEC 60958 output
•
Supports sampling frequencies from 16 to 100 kHz
•
Analog front-end includes a 0 to +24 dB PGA in steps of
3 dB, selectable via microcontroller interface
•
Digital independent left and right volume control of
+24 to
−63.5
dB in steps of 0.5 dB via microcontroller
interface
•
Bitstream ADC operating at 64f
s
•
Comb filter decreases sample rate from 64f
s
to 8f
s
•
Decimator filter (8f
s
to f
s
) made of a cascade of three FIR
half-band filters.
1.7
DAC digital sound processing
•
CMOS output level converted to IEC 60958 output
signal
•
Full-swing digital signal, with level II timing using crystal
oscillator clock
•
32, 44.1 and 48 kHz output frequencies supported in
static mode
•
Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio
sampling frequencies
•
Automatic de-emphasis when using IEC 60958 to DAC
•
Soft mute made of a cosine roll-off circuit selectable via
pin MUTE or L3-bus interface
3
2003 Apr 10
NXP Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
•
Programmable digital silence detector
•
Interpolating filter (f
s
to 64f
s
or f
s
to 128f
s
) comprising a
recursive and a FIR filter in cascade
•
Selectable fifth-order noise shaper operating at 64f
s
or
third-order noise shaper operating at 128f
s
(specially for
low sampling frequencies, e.g. 16 kHz) generating
bitstream for DAC
•
Filter Stream DAC (FSDAC)
•
In microcontroller mode:
– Left and right volume control (for balance control)
0 to
−78
dB and
−∞
– Left and right bass boost and treble control
– Optional resonant bass boost control
– Mixing possibility of two data streams.
2
GENERAL DESCRIPTION
UDA1355H
which can generate level II output signals with CMOS
levels. In microcontroller mode the UDA1355H offers a
large variety of possibilities for defining signal flows
through the IC, offering a flexible analog, digital and SPDIF
converter chip with possibilities for off-chip sound
processing via the digital input and output interface.
A lock indicator is available on pin LOCK when the
IEC 60958 decoder and the clock regeneration
mechanism is in lock. By default the DAC output and the
digital data interface output are muted when the decoder is
not in lock.
The UDA1355H contains two clock systems which can run
at independent frequencies, allowing to lock-on to an
incoming SPDIF or digital audio signal, and in the mean
time generating a stable signal by means of the crystal
oscillator for driving, for example, the ADC or SPDIF
output signal.
Using the crystal oscillator (which requires a 12.288 MHz
crystal) and the on-chip low jitter PLL, all standard audio
sampling frequencies (f
s
= 32, 44.1 and 48 kHz including
half and double these frequencies) can be generated.
The UDA1355H is a single-chip IEC 60958 decoder and
encoder with integrated stereo digital-to-analog converters
and analog-to-digital converters employing bitstream
conversion techniques.
The UDA1355H has a selectable one-of-four SPDIF input
(accepting level I, II and III timing) and one SPDIF output
3
ORDERING INFORMATION
TYPE
NUMBER
UDA1355H
PACKAGE
NAME
QFP44
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm); body
10
×
10
×
1.75 mm
VERSION
SOT307-2
2003 Apr 10
4
NXP Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
4
QUICK REFERENCE DATA
SYMBOL
Supplies
V
DDA1
V
DDA2
V
DDX
V
DDI
V
DDE
I
DDA1
DAC supply voltage
ADC supply voltage
crystal oscillator and PLL
supply voltage
digital core supply voltage
digital pad supply voltage
DAC supply current
f
s
= 48 kHz; power-on
f
s
= 96 kHz; power-on
f
s
= 48 kHz; power-down
f
s
= 96 kHz; power-down
I
DDA2
ADC supply current
f
s
= 48 kHz; power-on
f
s
= 96 kHz; power-on
f
s
= 48 kHz; power-down
f
s
= 96 kHz; power-down
I
DDX
I
DDI
I
DDE
T
amb
crystal oscillator and PLL
supply current
digital core supply current
digital pad supply current
ambient temperature
f
s
= 48 kHz; power-on
f
s
= 96 kHz; power-on
f
s
= 48 kHz; all on
f
s
= 96 kHz; all on
f
s
= 48 kHz; all on
f
s
= 96 kHz; all on
Digital-to-analog converter; f
i
= 1 kHz; V
DDA1
= 3.0 V
V
o(rms)
ΔV
o
(THD+N)/S
output voltage (RMS
value)
output voltage unbalance
total harmonic
distortion-plus-noise to
signal ratio
IEC 60958 input; f
s
= 48 kHz
at 0 dB
at
−20
dB
at
−60
dB; A-weighted
IEC 60958 input; f
s
= 96 kHz
at 0 dB
at
−60
dB; A-weighted
S/N
signal-to-noise ratio
IEC 60958 input; code = 0;
A-weighted
f
s
= 48 kHz
f
s
= 96 kHz
α
cs
channel separation
−
−
−
98
96
100
−
−
−83
−37
−
−
−
−88
−75
−37
−
−
900
0.1
2.7
2.7
2.7
2.7
2.7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−40
3.0
3.0
3.0
3.0
3.0
4.7
4.7
1.7
1.7
10.2
10.4
0.2
0.2
0.9
1.2
18.2
34.7
0.5
0.7
−
PARAMETER
CONDITIONS
MIN.
UDA1355H
TYP.
MAX.
UNIT
3.6
3.6
3.6
3.6
3.6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
+85
−
−
−
−
−
−
−
V
V
V
V
V
mA
mA
μA
μA
mA
mA
μA
μA
mA
mA
mA
mA
mA
mA
°C
mV
dB
dB
dB
dB
dB
dB
−
−
−
dB
dB
dB
2003 Apr 10
5
