PRELIMINARY DATA SHEET
μ
PC844GR-9LG, 4744GR-9LG
SINGLE SUPPLY VOLTAGE, HIGH SPEED,
WIDE BAND, DUAL OPERATIONAL AMPLIFIERS
BIPOLAR ANALOG INTEGRATED CIRCUIT
DESCRIPTION
The
μ
PC844GR-9LG, 4744GR-9LG are quad high speed, wide band operational amplifiers designed for single
supply operation from +3 V to +32 V with low supply current drain. By using high speed PNP transistors for input and
output circuits, the excellent AC performance is achieved without degrading capacitive load drive capability.
With no crossover distortion and wide output voltage range characteristics, the
μ
PC844GR-9LG, 4744GR-9LG are
optimum choice for single supply AC amplifier, and active filters.
FEATURES
•
High slew rate: 8.5 V/
μ
s TYP. (V
+
= +5 V, V
−
= GND)
•
Wide gain band width product: 3.5 MHz TYP. (V
+
= +5 V, V
−
= GND)
•
Wide supply voltage range: +3 V to +32 V
•
Wide output voltage swing
•
Common mode input voltage range includes V
−
•
Internal frequency compensation
•
Output short circuit protection
EQUIVALENT CIRCUIT (1/4 Circuit)
V
+
Q
7
Q
8
Q
9
Q
10
Q
11
Q
12
PIN CONFIGURATION
(Top View)
OUT
1
1
Q
2
I
I
I
N
Q
14
Q
20
Q
1
Q
3
Q
4
Q
18
14 OUT
4
1
– +
4
+ –
I
I1
2
Q
19
13 I
I4
12 I
N4
11 V
–
10 I
N3
I
N1
3
OUT
V
+
4
I
N2
5
I
I2
6
OUT
2
7
– +
2
+ –
3
Q
5
V
–
Q
6
Q
13
Q
15
Q
16
Q
17
9 I
I3
8 OUT
3
ORDERING INFORMATION
Part Number
Package
14-pin plastic TSSOP (5.72 mm (225))
14-pin plastic TSSOP (5.72 mm (225))
μ
PC844GR-9LG-A
μ
PC4744GR-9LG-A
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G17928EJ3V0DS00 (3rd edition)
Date Published April 2007 NS CP(N)
Printed in Japan
2006
μ
PC844GR-9LG, 4744GR-9LG
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Parameter
Voltage between V
+
and V
−
Differential Input Voltage
Input Voltage
Note 2
Note 3
Note 4
Note 5
Note 1
Symbol
V
+
−
V
−
V
ID
V
I
V
O
P
T
μ
PC844GR-9LG
μ
PC4744GR-9LG
Unit
V
V
V
V
mW
sec
−0.3
to +36
±36
V
−
−
0.3 to V
−
+ 36
V
−
−
0.3 to V
+
+ 0.3
550
Indefinite
Output Voltage
Power Dissipation
Output Short Circuit Duration
Operating Ambient Temperature
Storage Temperature
T
A
T
stg
−40
to +125
−55
to +150
−40
to +85
−55
to +125
°C
°C
Notes 1.
Reverse connection of supply voltage can cause destruction.
2.
The input voltage should be allowed to input without damage or destruction independent of the magnitude of
V
+
. Either input signal should not be allowed to go negative by more than 0.3 V. The normal operation will
establish when the both inputs are within the Common Mode Input Voltage Range of electrical
characteristics.
3.
This specification is the voltage which should be allowed to supply to the output terminal from external
without damage or destructive. Even during the transition period of supply voltage, power on/off etc., this
specification should be kept. The output voltage of normal operation will be the Output Voltage Swing of
electrical characteristics.
4.
The thermal deleting factor of these IC are same value as –7.0 mW/°C, but the delete beginning temperature
in different as follows.
μ
PC844GR-9LG : 71°C
μ
PC4744GR-9LG : 46°C
The calculated junction to ambient thermal resistance at above conditions is 144°C/W.
5.
Pay careful attention to the total power dissipation not to exceed the absolute maximum ratings, Note 4.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Split)
Supply Voltage (V
−
= GND)
Output Current
Capacitive Load (A
V
= +1, R
f
= 0
Ω)
Symbol
V
±
V
+
I
O
C
L
MIN.
±1.5
+3
TYP.
MAX.
±16
+32
±10
1000
Unit
V
V
mA
pF
2
Preliminary Data Sheet G17928EJ3V0DS
μ
PC844GR-9LG, 4744GR-9LG
ELECTRICAL CHARACTERISTICS (T
A
= 25 °C, V
±
= ±15 V)
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Note 6
Symbol
V
IO
I
IO
I
B
A
V
I
CC
CMR
SVR
V
om
V
om
V
ICM
SR
GBW
R
L
≥
10 kΩ
R
L
≥
2 kΩ
Conditions
MIN.
TYP.
±1.0
±6
140
MAX.
±6.0
±75
500
Unit
mV
nA
nA
Large Signal Voltage Gain
Supply Current
Note 7
R
L
≥
2 kΩ, V
O
= ±10 V
I
O
= 0 A
25000
300000
7.5
11
mA
dB
dB
V
V
V
+
−
1.8
8.5
3.5
120
V
V/
μ
s
MHz
dB
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Output Voltage Swing
Output Voltage Swing
Common Mode lnput Voltage Range
Slew Rate (Rise)
Gain Band Width Product
Channel Separation
70
70
±13.7
±13.5
V
−
A
V
= 1, R
L
≥
2 kΩ
f
O
= 100 kHz
f = 20 Hz to 20 kHz
86
93
+14
−14.3
ELECTRICAL CHARACTERISTICS (T
A
= 25 °C, V
+
= 5 V, V
–
= GND)
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Note 6
Symbol
V
IO
I
IO
I
B
A
V
I
CC
CMR
SVR
V
om
R
L
≥
2 kΩ
I
O
= 0 A
Conditions
MIN.
TYP.
±1.0
±6
160
MAX.
±5
±75
500
Unit
mV
nA
nA
Large Signal Voltage Gain
Supply Current
Note 7
25000
300000
6.0
9.0
mA
dB
dB
V
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Output Voltage Swing
70
70
R
L
≥
2 kΩ (Connect to GND)
3.7
0
80
95
4.0
0
V
+
−
1.8
30
30
8.5
Common Mode lnput Voltage Range
Output Current (SOURCE)
Output Current (SINK)
Slew Rate (Rise)
V
ICM
I
O SOURCE
I
O SINK
SR
V
+IN
= +1 V, V
−
IN
= 0 V
V
+IN
= 0 V, V
−
IN
= +1 V
A
V
= 1, R
L
≥
2 kΩ
0
10
10
V
mA
mA
V/
μ
s
Notes 6.
Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input
stage.
7.
This current flows irrespective of the existence of use.
Preliminary Data Sheet G17928EJ3V0DS
3
μ
PC844GR-9LG, 4744GR-9LG
PACKAGE DRAWINGS
14-PIN PLASTIC TSSOP (5.72mm (225))
D
D1
detail of lead end
A3
14
8
c
θ
1
7
L
Lp
(UNIT:mm)
ZD
b
x
M
e
S
ITEM
D
D1
E
HE
DIMENSIONS
5.15±0.15
5.00±0.10
4.40±0.10
6.40±0.20
1.20 MAX.
0.10±0.05
1.00±0.05
0.25
+0.06
0.24
−0.05
0.145±0.055
0.50
0.60±0.15
1.00±0.20
3°
+5°
−3°
0.65
0.10
0.10
0.625
P14GR-65-9LG
HE
A
A2
S
E
L1
A
A1
A2
A3
b
c
L
Lp
L1
y
S
A1
θ
NOTE
Each lead centerline is located within 0.10mm of
its true position at maximum material condition.
e
x
y
ZD
4
Preliminary Data Sheet G17928EJ3V0DS
μ
PC844GR-9LG, 4744GR-9LG
RECOMMENDED SOLDERING CONDITIONS
The
μ
PC844GR-9LG, 4744GR-9LG should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Surface Mount Device
Process
Infrared ray reflow
Conditions
Peak temperature: 260 °C or below (Package surface temperature),
Reflow time: 60 seconds or less (at 220 °C or higher),
Maximum number of reflow processes: 3 time.
Solder temperature: 260 °C or below, Flow time: 10 seconds or less,
Maximum number of flow processes: 1 time,
Pre-heating temperature: 120 °C or below (Package surface temperature).
Pin temperature: 350 °C or below,
Heat time: 3 seconds or less (Per each side of the device).
Symbol
IR60-00-3
Wave soldering
WS60-00-1
Partial heating method
P350
Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or the
device will be damaged by heat stress.
REFERENCE DOCUMENTS
Document Name
QUALITY GRADES ON NEC SEMICONDUCTOR DEVICES
SEMICONDUCTOR DEVICE MOUNT MANUAL
NEC SEMICONDUCTOR DEVICE RELIABILITY/QUALITY CONTROL SYSTEM
- STANDARD LINEAR IC
C11531E
http://www.necel.com/pkg/en/mount/index.html
IEI-1212
Document No.
Preliminary Data Sheet G17928EJ3V0DS
5
