DATA
DATA
PRELIMINARY PRODUCTSHEET
PRELIMINARY
SHEET
INFORMATION
MOS INTEGRATED CIRCUIT
µ
PD30550
V
R
5500
TM
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The
µ
PD30550 (V
R
5500) is a member of the V
R
Series
TM
of RISC (Reduced Instruction Set Computer)
microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed
by MIPS
TM
.
The V
R
5500 allows selection of a 64-bit or 32-bit bus width for the system interface, and can operate using
protocols compatible with the V
R
5000 Series and V
R
5432 .
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual
before designing.
•
V
R
5500 User’s Manual (U16044E)
TM
TM
FEATURES
•
MIPS 64-bit RISC architecture
•
High-speed operation processing
•
Two-way superscalar super pipeline
•
300 MHz product:
400 MHz product:
(48 entries)
•
Address space
•
Physical:
•
Virtual:
36 bits (64-bit bus selected)
32 bits (32-bit bus selected)
40 bits (in 64-bit mode)
31 bits (in 32-bit mode)
•
On-chip floating-point unit (FPU)
•
Supports sum-of-products instructions
•
On-chip primary cache memory
(instruction/data: 32 KB each)
•
2-way set associative
•
Supports line lock feature
603 MIPS
804 MIPS
•
64-/32-bit address/data multiplexed bus
•
Bus width selectable during reset
•
Bus protocol compatibility with existing products
retained
•
Maximum operating frequency
•
300 MHz product: Internal 300 MHz, external 133
MHz
400 MHz product: Internal 400 MHz, external 133
MHz
•
External/internal multiplication factor selectable from
×2
to
×5.5
by increments of 0.5
•
Conforms to MIPS I, II, III, and IV instruction sets. Also
supports product-sum operation instruction, rotate
instruction, register scan instruction, and instruction for
low power mode.
•
Supports hardware debug function (N-Wire)
•
Supply voltage
Core block:
I/O block:
1.5 V
±5%
(300 MHz product)
1.6 to 1.7 V (400 MHz product)
3.3 V
±5%,
2.5 V
±5%
•
High-speed translation lookaside buffer (TLB)
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U15700EJ1V1DS00 (1st edition)
Date Published October 2002 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
2002
2001
µ
PD30550
APPLICATIONS
•
Set-top boxes
•
RAID
•
High-end embedded devices, etc.
ORDERING INFORMATION
Part Number
Package
272-pin plastic BGA (C/D advanced type) (29
×
29)
272-pin plastic BGA (C/D advanced type) (29
×
29)
Maximum Operating Frequency (MHz)
300
400
µ
PD30550F2-300-NN1
µ
PD30550F2-400-NN1
PIN CONFIGURATION
•
272-pin plastic BGA (C/D advanced type) (29
×
29)
µ
PD30550F2-300-NN1
µ
PD30550F2-400-NN1
Bottom View
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AA Y W V U T R P N M L K J H G F E D C B A
Top View
A B C D E F G H J K L M N P R T U V W Y AA
Index mark
2
Preliminary Data Sheet U15700EJ1V1DS
µ
PD30550
(1/2)
No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
V
SS
V
SS
V
DD
IO
V
DD
IO
Reset#
PReq#
ValidIn#
ValidOut#
V
SS
SysADC7
SysADC3
SysADC1
SysADC4
SysAD62
SysAD30
SysAD28
SysAD59
V
DD
IO
V
DD
IO
V
SS
V
SS
V
SS
V
SS
V
DD
IO
V
DD
IO
ColdReset#
Release#
ExtRqst#
BusMode
SysID2
V
DD
SysADC6
V
SS
SysADC0
V
DD
SysAD61
V
SS
Pin Name
No.
B17
B18
B19
B20
B21
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Pin Name
SysAD27
V
DD
IO
V
DD
IO
V
SS
V
SS
V
DD
IO
V
DD
IO
V
SS
V
SS
V
SS
V
DD
WrRdy#
V
SS
SysID1
V
DD
SysADC2
V
SS
SysAD63
V
DD
SysAD29
V
SS
SysAD58
V
DD
IO
V
SS
V
DD
IO
V
DD
IO
V
DD
IO
V
DD
IO
V
SS
V
SS
IC
V
DD
RdRdy#
V
SS
SysID0
V
DD
SysADC5
No.
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
E1
E2
E3
E4
E18
E19
E20
E21
F1
F2
F3
F4
F18
F19
F20
F21
G1
G2
G3
G4
G18
G19
G20
G21
H1
H2
H3
V
SS
SysAD31
V
DD
SysAD60
V
SS
SysAD26
V
SS
V
SS
V
DD
IO
V
DD
IO
SysCmd0
DisDValidO#
DWBTrans#
O3Return#
SysAD57
SysAD25
SysAD56
SysAD24
SysCmd1
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
SysAD55
SysCmd2
SysCmd3
SysCmd4
SysCmd5
SysAD23
SysAD54
SysAD22
SysAD53
SysCmd6
V
DD
V
DD
Pin Name
No.
H4
H18
H19
H20
H21
J1
J2
J3
J4
J18
J19
J20
J21
K1
K2
K3
K4
K18
K19
K20
K21
L1
L2
L3
L4
L18
L19
L20
L21
M1
M2
M3
M4
M18
M19
M20
M21
V
DD
V
SS
V
SS
V
SS
SysAD21
SysCmd7
SysCmd8
TIntSel
Int0#
SysAD52
SysAD20
SysAD51
SysAD19
Int1#
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
Int2#
Int3#
Int4#
Int5#
SysAD17
SysAD49
SysAD18
SysAD50
RMode#/BKTGIO#
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
Pin Name
Caution Leave the IC pin open.
Remark
# indicates active low.
Preliminary Data Sheet U15700EJ1V1DS
3
µ
PD30550
(2/2)
No.
N1
N2
N3
N4
N18
N19
N20
N21
P1
P2
P3
P4
P18
P19
P20
P21
R1
R2
R3
R4
R18
R19
R20
R21
T1
T2
T3
T4
T18
T19
T20
Pin Name
V
DD
IO
NMI#
V
DD
IO
BigEndian
SysAD15
SysAD47
SysAD16
SysAD48
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
SysAD46
DivMode0
DivMode1
DivMode2
V
DD
IO
SysAD44
SysAD13
SysAD45
SysAD14
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
No.
T21
U1
U2
U3
U4
U18
U19
U20
U21
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
W1
Pin Name
SysAD12
NTrcClk
NTrcData0
NTrcData1
NTrcData3
SysAD10
SysAD42
SysAD11
SysAD43
NTrcData2
NTrcEnd
V
SS
V
SS
V
SS
PA2
V
SS
V
DD
IO
V
DD
JTMS
V
SS
SysAD33
V
DD
SysAD4
V
SS
SysAD7
V
DD
SysAD41
V
SS
V
SS
V
DD
IO
V
DD
IO
V
DD
IO
No.
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Pin Name
V
DD
IO
V
SS
V
SS
V
DD
PA2
V
SS
V
DD
IO
V
DD
JTDI
V
SS
SysAD1
V
DD
SysAD35
V
SS
SysAD38
V
DD
SysAD9
V
SS
V
SS
V
DD
IO
V
DD
IO
V
SS
V
SS
V
DD
IO
V
DD
IO
V
SS
PA1
SysClock
JTRST# (V
SS
)
V
DD
JTCK
V
SS
SysAD32
No.
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
V
DD
SysAD3
V
SS
SysAD37
SysAD39
SysAD40
V
DD
IO
V
DD
IO
V
SS
V
SS
V
SS
V
SS
V
DD
IO
V
DD
IO
V
DD
PA1
V
DD
IO
IC
JTDO
DrvCon
V
SS
SysAD0
SysAD2
SysAD34
SysAD36
SysAD5
SysAD6
SysAD8
V
DD
IO
V
DD
IO
V
SS
V
SS
Pin Name
Caution Leave the IC pin open.
Remarks 1.
The name in parentheses indicates the pin name in the revision 1.x product.
2.
# indicates active low.
4
Preliminary Data Sheet U15700EJ1V1DS
µ
PD30550
PIN NAMES
BigEndian:
BKTGIO#:
BusMode:
ColdReset#:
DisDValidO#:
DivMode(2:0):
DrvCon:
DWBTrans#:
ExtRqst#:
IC
Int(5:0)#:
JTCK:
JTDI:
JTDO:
JTMS:
JTRST#:
NMI#:
NTrcClk:
NTrcData(3:0) :
NTrcEnd:
O3Return#:
Remark
Big endian
Break/trigger input/output
Bus mode
Cold reset
Disable delay ValidOut#
Divide mode
Driver control
Doubleword block transfer
External request
Internally connected
Interrupt
JTAG clock
JTAG data input
JTAG data output
JTAG mode select
JTAG reset
Non-maskable interrupt
N-Trace clock
N-Trace data output
N-Trace end
Out-of-Order Return mode
SysID(2:0):
TIntSel:
ValidIn#:
ValidOut#:
V
DD
:
V
DD
IO:
V
DD
PA1, V
DD
PA2:
V
SS
:
V
SS
PA1, V
SS
PA2:
WrRdy#:
SysClock:
SysCmd(8:0):
PReq#:
RdRdy#:
Release#:
Reset#:
SysAD(63:0):
SysADC(7:0):
Processor request
Read ready
Release
Reset
System address/data bus
System address/data check
bus
System clock
System command/data
identifier bus
System bus identifier
Timer interrupt selection
Valid input
Valid output
Power supply for CPU core
Power supply for I/O
Quiet V
DD
for PLL
Ground
Quiet V
SS
for PLL
Write ready
# indicates active low.
Preliminary Data Sheet U15700EJ1V1DS
5
