VRE3025
Low Cost
Precision Reference
THALER CORPORATION • 2015 N. FORBES BOULEVARD • TUCSON, AZ. 85745 • (520) 882-4000
FEATURES
•
2.500 V Output ± 0.250 mV (.01%)
•
Temperature Drift: 0.6 ppm/°C
•
Low Noise: 1.5
µ
V
p-p
(0.1Hz-10Hz)
•
Low Thermal Hysteresis: 1 ppm Typ.
•
±15mA Output Source and Sink Current
•
Excellent Line Regulation: 5 ppm/V Typ.
•
Optional Noise Reduction and Voltage Trim
•
Industry Standard Pinout
PIN CONFIGURATION
N/C
+V
IN
N/C
GND
1
2
3
4
8
NOISE
REDUCTION
N/C
V
OUT
TRIM
VRE3025
TOP
VIEW
7
6
5
FIGURE 1
DESCRIPTION
The VRE3025 is a low cost, high precision 2.5V
reference that operates from +10V. The device
features a buried zener for low noise and excellent
long term stability. Packaged in an 8 pin DIP and
SMT, the device is ideal for high resolution data
conversion systems.
The device provides ultrastable +2.500V output
with ±0.2500 mV (.01%) initial accuracy and a
temperature coefficient of 0.6 ppm/°C.
This
improvement in accuracy is made possible by a
unique, patented multipoint laser compensation
technique developed by Thaler Corporation.
Significant improvements have been made in
other performance parameters as well, including
initial accuracy, warm-up drift, line regulation, and
long-term stability, making the VRE3025 series
the most accurate reference available.
For enhanced performance, the VRE3025 has an
external trim option for users who want less than
0.01% initial error.
For ultra low noise
applications, an external capacitor can be
attached between the noise reduction pin and the
ground pin.
The VRE3025 is recommended for use as a
reference for 14, 16, or 18 bit data converters
which require an external precision reference.
The device is also ideal for calibrating scale factor
on high resolution data converters. The VRE3025
offers superior performance over monolithic
references.
SELECTION GUIDE
Initial
Error
mV
0.250
0.375
0.500
0.250
0.375
0.500
Model
VRE3025A
VRE3025B
VRE3025C
VRE3025J
VRE3025K
VRE3025L
Temp.
Coeff.
ppm/°C
0.6
1.0
2.0
0.6
1.0
2.0
Temp.
Range °C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
For package option add D for DIP or S for Surface Mount
to end of model number.
VRE3025DS REV.D JULY 2000
ABSOLUTE MAXIMUM RATINGS
Power Supply ………………………-0.3V to +40V
OUT, TRIM …………………………-0.3V to +12V
NR……………………………………-0.3V to +6V
Operating Temp. (
A,B,C
)……………0 °C to 70°C
Operating Temp. (
J,K,L
)……………-40 °C to 85°C
Out Short Circuit to GND Duration (V
IN
< 12V)…...Continuous
Out Short Circuit to GND Duration (V
IN
< 40V)…….……5 sec
Out Short Circuit to IN Duration (V
IN
< 12V)………Continuous
Continuous Power Dissipation (T
A
= +70°C)…….…...300mW
Storage Temperature……………………..……-65°C to 150°C
Lead Temperature (soldering,10 sec) ………………….250°C
ELECTRICAL SPECIFICATIONS
Vps =+10V, T = 25°C, Iout=0mA unless otherwise noted.
PARAMETER
Input Voltage
SYMBOL
V
IN
CONDITIONS
MIN
8
TYP
MAX
36
UNITS
V
VRE3025A/J
Output Voltage
(Note 1)
Output Voltage
Temperature Coefficient
(Note 2)
Trim Adjustment Range
Turn-On Settling Time
Output Noise Voltage
Temperature Hysterisis
Long Term Stability
Supply Current
Load Regulation
∆V
OUT/t
I
IN
∆V
OUT
/
∆I
OUT
Sourcing:
0mA
≤
I
OUT
≤
15mA
Sinking:
-15mA
≤
I
OUT
≤0mA
8V
≤
V
IN
≤
10V
10V
≤
V
IN
≤18V
V
OUT
VRE3025B/K
VRE3025C/L
VRE3025A/J
TCV
OUT
VRE3025B/K
VRE3025C/L
∆V
OUT
T
on
e
n
Figure 3
To 0.01% of final value
0.1Hz<f<10Hz
10Hz<f<1kHz
Note 4
2.4998
2.4996
2.4995
2.5000
2.5000
2.5000
0.3
0.5
1.0
±2.5
2
1.5
1.5
1
6
3.5
8
8
25
5
2.5003
2.5004
2.5005
0.6
1.0
2.0
mV
µs
µVp-p
3.0
µV
RMS
ppm
ppm/
1khrs
4.0
12
12
35
ppm/V
10
mA
ppm/
mA
ppm/°C
V
Line Regulation
∆V
OUT
/
∆V
IN
Notes:
1) The specified values are without external trim.
2) The temperature coefficient is determined by the
box method. See discussion on temperature
performance.
3) Line and load regulation are measured with pulses and
do not include voltage changes due to temperature.
4) Hysterisis over the operating temperature range.
VRE3025DS REV.D JULY 2000
TYPICAL PERFORMANCE CURVES
V
OUT
vs. TEMPERATURE
1.00
0.75
0.50
1.00
0.75
0.50
V
OUT
vs. TEMPERATURE
1.00
0.75
0.50
V
OUT
vs. TEMPERATURE
Upper
Limit
∆V
out
(mV)
∆V
out
(mV)
0.25
0
-0.25
-0.50
-0.75
-1.00
0
-0.25
-0.50
-0.75
-1.00
0
20
30
40
50
60
70
Lower Limit
Lower Limit
∆V
out
(mV)
0.25
Upper Limit
Upper Limit
Upper
Limit
0.25
0
-0.25
-0.50
-0.75
Lower
Limit
Lower
Limit
0
20
30
40
50
60
70
-1.00
0
20
30
40
50
60
70
Temperature (
o
C)
VRE3025A
Temperature (
o
C)
VRE3025B
Temperature (
o
C)
VRE3025C
V
OUT
vs. TEMPERATURE
2.0
1.5
1.0
Upper
Limit
V
OUT
vs. TEMPERATURE
2.0
1.5
1.0
Upper
Limit
V
OUT
vs. TEMPERATURE
2.0
1.5
Upper
Limit
1.0
∆V
out
(mV)
∆V
out
(mV)
0
-0.5
-1.0
-1.5
-2.0
-50 -25
Lower
Limit
0
-0.5
-1.0
-1.5
-2.0
-50 -25
Lower
Limit
∆V
out
(mV)
0.5
0.5
0.5
0
-0.5
-1.0
-1.5
-2.0
-50 -25
Lower
Limit
0
25
50
75 100
0
25
50
75 100
0
25
50
75 100
Temperature (
o
C)
VRE3025J
Temperature (
o
C)
VRE3025K
Temperature (
o
C)
VRE3025L
SUPPLY CURRENT
VS. SUPPLY VOLTAGE
6.0
QUIESCENT CURRENT VS. TEMP
8.0
OUTPUT IMPEDIANCE
VS. FREQUENCY
Quiescent Current (mA)
5.0
4.0
6.0
4.0
2.0
0
3.0
0
0
5 10 15 20 25 30 35 40
-50
0
50
100
Output Impediance (
Ω)
Supply Current (mA)
Supply Voltage (V)
Temperature (
o
C)
Frequency (Hz)
VRE3025DS REV.D JULY 2000
TYPICAL PERFORMANCE CURVES
40
JUNCTION TEMP. RISE VS.
OUTPUT CURRENT
Ripple Rejection (dB)
100
90
80
70
60
10
RIPPLE REJECTION
Vs. FREQUENCY(C
NR
=0µF)
A
TURN-ON AND TURN-OFF
TRANSIENT RESPONSE
+10V
0V
Junction Temperature
Rise Above Ambient (
o
C)
30
20
Vc
10
0
c
=
V
10
B
0
2
4
6
8
10
100
1k
10k
Output Current (mA)
Frequency (Hz)
1
µs/div
A: Vin, 10V/div
B: Vout, 1V/div
OUTPUT NOISE-VOLTAGE
DENSITY vs. FREQUENCY
Output Noise Density (nV/√Hz)
50
40
CHANGE IN OUTPUT VOLTAGE
VS. OUTPUT CURRENT
400
300
100
0
-100
-200
-300
-400
200
CHANGE IN OUTPUT VOLTAGE
VS. INPUT VOLTAGE
60
50
40
30
20
10
0
-10
-20
30
20
10
10
100
1k
10k
0 2
4
6
8 10 12 14 16
Vout (ppm)
Vout (µV)
0
9 10 11 12 13 14 15 16
Frequency (Hz)
I
out
(mA)
V
in
(V)
0.1Hz to 10Hz Noise
∆Vout,
0.5µV/Div
1 Sec/Div
VRE3025DS REV.D JULY 2000
THEORY OF OPERATION
The following discussion refers to the schematic in
figure 2 below. A FET current source is used to bias a
6.3V zener diode. The zener voltage is divided by the
resistor network R1 and R2. This voltage is then applied
to the noninverting input of the operational amplifier which
amplifies the voltage to produce a 2.500V output. The
gain is determined by the resistor networks R3 and R4:
G=1 + R4/R3. The 6.3V zener diode is used because it is
the most stable diode over time and temperature.
8
2
BASIC CIRCUIT CONNECTION
Figure 3 shows the proper connection of the VRE3025
voltage reference with the optional trim resistor for initial
error and optional capacitor for noise reduction.
+ V
IN
2
8
C
N
1µF
Optional Noise
Reduction
Capacitor
VRE3025
5
4
Optional Fine
Trim Adjustment
6
+ V
OUT
10kΩ
+
R1
R4
R2
R3
6
-
Figure 3 External Connections
5
4
To achieve the specified performance, pay careful
attention to the layout. A low resistance star configuration
will reduce voltage errors, noise pickup, and noise
coupled from the power supply. Commons should be
connected to a single point to minimize interconnect
resistances.
Figure 2 Functional Block Diagram
The current source provides a closely regulated zener
current, which determines the slope of the references’
voltage vs. temperature function. By trimming the zener
current a lower drift over temperature can be achieved.
But since the voltage vs. temperature function is nonlinear
this compensation technique is not well suited for wide
temperature ranges.
Thaler Corporation has developed a nonlinear
compensation network of thermistors and resistors that is
used in the VRE series voltage references. This
proprietary network eliminates most of the nonlinearity in
the voltage vs. temperature function. By adjusting the
slope, Thaler Corporation produces a very stable voltage
over wide temperature ranges.
This network is less than 2% of the overall network
resistance so it has a negligible effect on long term
stability. Figure 3 shows the proper connection of the
VRE3025 series voltage references with the optional trim
resistor for initial error and the optional capacitor for noise
reduction.
PIN DESCRIPTION
1,3,7
2
4
5
6
8
N.C.
Vin
GND
TRIM
OUT
NR
Internally connected. Do not use
Positive power supply input
Ground
External trim input. Leave open if
not used.
Voltage reference output
Noise Reduction
VRE3025DS REV.D JULY 2000
FPGA/CPLD
