VS-P100 Series
www.vishay.com
Vishay Semiconductors
Power Modules,
Passivated Assembled Circuit Elements, 25 A
FEATURES
• Glass passivated junctions for greater reliability
• Electrically isolated base plate
• Available up to 1200 V
RRM
/V
DRM
• High dynamic characteristics
• Wide choice of circuit configurations
• Simplified mechanical design and assembly
• UL E78996 approved
PACE-PAK (D-19)
• Material categorization: For definitions of compliance
please see
www.vishay.com/doc?99912
DESCRIPTION
PRODUCT SUMMARY
I
O
Type
Package
Circuit
25 A
Modules - Thyristor, Standard
PACE-PAK (D-19)
Single phase, hybrid bridge common cathode,
Single phase, hybrid bridge doubler connection,
Single phase, all SCR bridge
The VS-P100 series of integrated power circuits consists of
power thyristors and power diodes configured in a single
package. With its isolating base plate, mechanical designs
are greatly simplified giving advantages of cost reduction
and reduced size.
Applications include power supplies, control circuits and
battery chargers.
MAJOR RATINGS AND CHARACTERISTICS
SYMBOL
I
O
I
TSM
I
2
t
I
2
t
V
DRM
, V
RRM
V
ISOL
T
J
T
Stg
Range
CHARACTERISTICS
85 °C
50 Hz
60 Hz
50 Hz
60 Hz
VALUES
25
357
375
637
580
6365
400 to 1200
2500
-40 to 125
-40 to 125
UNITS
A
A
A
2
s
A
2
s
V
V
°C
°C
ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
TYPE NUMBER
VS-P101, VS-P121, VS-P131
VS-P102, VS-P122, VS-P132
VS-P103, VS-P123, VS-P133
VS-P103, VS-P124, VS-P134
VS-P105, VS-P125, VS-P135
V
RRM
/V
DRM
, MAXIMUM
REPETITIVE PEAK REVERSE AND
PEAK OFF-STATE VOLTAGE
V
400
600
800
1000
1200
V
RSM
, MAXIMUM
NON-REPETITIVE PEAK
REVERSE VOLTAGE
V
500
700
900
1100
1300
10
I
RRM
MAXIMUM
AT T
J
MAXIMUM
mA
Revision: 27-Mar-14
Document Number: 93754
1
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-P100 Series
www.vishay.com
Vishay Semiconductors
ON-STATE CONDUCTION
PARAMETER
Maximum DC output current at case
temperature
SYMBOL
I
O
Full bridge
t = 10 ms
Maximum peak, one-cycle non-repetitive
on-state or forward current
I
TSM
,
I
FSM
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 10 ms
Maximum I
2
t for fusing
I
2
t
t = 8.3 ms
t = 10 ms
t = 8.3 ms
Maximum I
2
t
for fusing
Maximum value of threshold voltage
Maximum level value of on-state slope
resistance
Maximum on-state voltage drop
Maximum forward voltage drop
Maximum non-repetitive rate of rise of
turned-on current
Maximum holding current
Maximum latching current
I
2
t
V
T(TO)
r
t1
V
TM
V
FM
dI/dt
I
H
I
L
No voltage
reapplied
100 % V
RRM
reapplied
No voltage
reapplied
100 % V
RRM
reapplied
TEST CONDITIONS
VALUES
25
85
357
375
300
Sinusoidal half wave,
initial T
J
= T
J
maximum
315
637
580
450
410
6365
0.82
12
1.35
1.35
200
130
250
A
2
s
V
m
V
V
A/μs
mA
A
2
s
A
UNITS
A
°C
t = 0.1 ms to 10 ms, no voltage reapplied
I
2
t for time tx = I
2
t
·
tx
T
J
= 125 °C
T
J
= 125 °C, average power = V
T(TO)
x I
T(AV)
+ r
t
+ (I
T(RMS)
)
2
I
TM
=
x I
T(AV)
I
FM
=
x I
F(AV)
T
J
= 25 °C
T
J
= 25 °C
T
J
= 125 °C from 0.67 V
DRM
I
TM
=
x I
T(AV)
, I
g
= 500 mA, t
r
< 0.5 μs, t
p
> 6 μs
T
J
= 25 °C anode supply = 6 V, resistive load, gate open
T
J
= 25 °C anode supply = 6 V, resistive load
BLOCKING
PARAMETER
Maximum critical rate of rise of off-state
voltage
Maximum peak reverse and off-state
leakage current at V
RRM
, V
DRM
Maximum peak reverse leakage current
RMS isolation voltage
SYMBOL
dV/dt
I
RRM
,
I
DRM
I
RRM
V
ISOL
TEST CONDITIONS
T
J
= 125 °C, exponential to 0.67 V
DRM
gate open
T
J
= 125 °C, gate open circuit
T
J
= 25 °C
50 Hz, circuit to base, all terminals shorted,
T
J
= 25 °C, t = 1 s
VALUES
200
10
100
2500
UNITS
V/μs
mA
μA
V
TRIGGERING
PARAMETER
Maximum peak gate power
Maximum average gate power
Maximum peak gate current
Maximum peak negative gate voltage
Maximum gate voltage required to trigger
SYMBOL
P
GM
P
G(AV)
I
GM
-V
GM
T
J
= - 40 °C
V
GT
T
J
= 25 °C
T
J
= 125 °C
T
J
= - 40 °C
Maximum gate current required to trigger
Maximum gate voltage that will not trigger
Maximum gate current that will not trigger
I
GT
V
GD
I
GD
T
J
= 25 °C
T
J
= 125 °C
T
J
= 125 °C, rated V
DRM
applied
Anode supply =
6 V resistive load
TEST CONDITIONS
VALUES
8
2
2
10
3
2
1
90
60
35
0.2
2
V
mA
mA
V
UNITS
W
A
V
Revision: 27-Mar-14
Document Number: 93754
2
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-P100 Series
www.vishay.com
Vishay Semiconductors
THERMAL AND MECHANICAL SPECIFICATIONS
PARAMETER
Maximum junction operating
and storage temperature range
Maximum thermal resistance,
junction to case per junction
Maximum thermal resistance,
case to heatsink
Mounting torque, base to heatsink
(1)
Approximate weight
Case style
SYMBOL
T
J
, T
Stg
R
thJC
R
thCS
DC operation
Mounting surface, smooth and greased
TEST CONDITIONS
VALUES
-40 to 125
2.24
K/W
0.10
4
58
2.0
Nm
g
oz.
UNITS
°C
PACE-PAK (D-19)
Note
(1)
A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound
60
60
~
-
Maximum Total Power Loss (W)
Maximum Total Power Loss (W)
+
50
40
30
20
10
T
J
= 125 °C
0
0
5
10
15
20
25
180°
(sine)
50
40
30
R
th
S
A
2K
=
/W
/W
15
K/
W
3K
-
Δ
R
5 K/
20
10
0
0
W
7 K/W
10 K/W
25
50
75
100
125
93754_01a
Total Output Current (A)
93754_01b
Maximum Allowable
Ambient Temperature (°C)
Fig. 1 - Current Ratings Nomogram (1 Module Per Heatsink)
15
20
Maximum Average On-State
Power Loss (W)
Maximum Average On-State
Power Loss (W)
10
180°
120°
90°
60°
30°
15
RMS limit
DC
180°
120°
90°
60°
30°
RMS limit
10
5
Ø
Conduction angle
T
J
= 125 °C
Per junction
0
0
5
10
15
5
Ø
Conduction period
T
J
= 125 °C
Per junction
0
5
10
15
20
0
93754_02
Average On-State Current (A)
Fig. 2 - On-State Power Loss Characteristics
93754_03
Average On-State Current (A)
Fig. 3 - On-State Power Loss Characteristics
Revision: 27-Mar-14
Document Number: 93754
3
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-P100 Series
www.vishay.com
Vishay Semiconductors
350
At any rated load condition and with
rated V
RRM
applied following
surge.
Initial T
J
= 125 °C
at 60 Hz 0.0083
s
at 50 Hz 0.0100
s
130
Fully turned-on
Maximum Allowable Case
Temperature (°C)
120
Peak Half
Sine
Wave
On-State Current (A)
300
110
100
90
80
Per module
70
0
5
10
15
180°
(Sine)
180°
(Rect.)
250
200
Per junction
150
20
25
30
93754_06
1
10
100
93754_04
Total Output Current (A)
Fig. 4 - Current Ratings Characteristics
Number of Equal Amplitude Half
Cycle Current Pulses (N)
Fig. 6 - Maximum Non-Repetitive Surge Current
Instantaneous On-State Current (A)
1000
T
J
= 25 °C
400
350
Maximum non-repetitive
surge
current
versus pulse train duration. Control of
conduction may not be maintained.
Initial T
J
= 125 °C
No voltage reapplied
Rated V
RRM
reapplied
100
T
J
= 125 °C
Peak Half
Sine
Wave
On-State Current (A)
300
250
200
150
10
Per junction
1
0
1
2
3
4
5
6
Per junction
100
0.01
93754_07
0.1
1
93754_05
Instantaneous On-State Voltage (V)
Fig. 5 - On-State Voltage Drop Characteristics
Pulse Train Duration (s)
Fig. 7 - Maximum Non-Repetitive Surge Current
10
Z
thJC
- Transient Thermal
Impedance (K/W)
Steady state
value
R
thJC
= 2.24 K/W
(DC operation)
1
0.1
Per junction
0.01
0.0001
0.001
0.01
0.1
1
10
93754_08
Square
Wave Pulse Duration (s)
Fig. 8 - Thermal Impedance Z
thJC
Characteristics
Revision: 27-Mar-14
Document Number: 93754
4
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-P100 Series
www.vishay.com
Vishay Semiconductors
(1) P
GM
= 10 W, t
p
= 5 ms
(2) P
GM
= 20 W, t
p
= 25 ms
(3) P
GM
= 50 W, t
p
= 1 ms
(4) P
GM
= 100 W, t
p
= 500 μs
(a)
(b)
T
J
= 25 °C
T
J
= 125 °C
T
J
= 40 °C
100
Instantaneous
Gate
Voltage (V)
10
Rectangular gate pulse
(a) Recommended load line for
rated dI/dt: 10 V, 20
Ω,
t
r
≤ 1 μs
(b) Recommended load line for
rated dI/dt: 10 V, 65
Ω,
t
r
≤ 1 μs
1
V
GD
I
GD
0.01
(1)
(2)
(3)
(4)
Frequency limited by P
G(AV)
0.1
1
10
100
0.1
0.001
93754_09
Instantaneous
Gate
Current (A)
Fig. 9 - Gate Characteristics
ORDERING INFORMATION TABLE
Device code
VS-
1
1
2
3
P
2
-
-
-
1
3
0
4
2
5
K
6
W
7
Vishay Semiconductors product
Module type
Current rating
1 = 25 A DC (P100 Series)
4 = 40 A DC (P400 Series)
Circuit configuration
0 = Single Phase, Hybrid Bridge Common Cathode
2 = Single Phase, Hybrid Bridge Doubler Connection
3 = Single Phase, all SCR Bridge
Voltage code
1 = 400 V
2 = 600 V
3 = 800 V
4 = 1000 V
5 = 1200 V
K = Optional Voltage Suppression
W = Optional Freewheeling Diode
4
-
5
-
6
7
-
-
Revision: 27-Mar-14
Document Number: 93754
5
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
