W49F002U Data Sheet
256K
×
8 CMOS FLASH MEMORY
Table of Content-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
PIN CONFIGURATIONS............................................................................................................. 4
BLOCK DIAGRAM ...................................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 4
FUNCTIONAL DESCRIPTION.................................................................................................... 5
6.1
Device Operation ............................................................................................................ 5
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
Read Mode.......................................................................................................................5
Write Mode .......................................................................................................................5
Standby Mode ..................................................................................................................5
Output Disable Mode........................................................................................................5
Auto-select Mode..............................................................................................................5
Reset Mode: Hardware Reset ..........................................................................................6
Low VDD Inhibit................................................................................................................6
Write Pulse "Glitch" Protection .........................................................................................6
Logical Inhibit ...................................................................................................................6
Power-up Write and Read Inhibit......................................................................................6
Read Command ...............................................................................................................7
Auto-select Command ......................................................................................................7
Byte Program Command ..................................................................................................7
Chip Erase Command ......................................................................................................8
Sector Erase Command ...................................................................................................8
DQ7: Data Polling.............................................................................................................8
DQ6: Toggle Bit ................................................................................................................9
6.2
Data Protection ............................................................................................................... 6
6.2.1
6.2.2
6.2.3
6.2.4
6.3
Command Definitions ..................................................................................................... 7
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
Write Operation Status ................................................................................................... 8
6.4.1
6.4.2
7.
8.
TABLE OF OPERATING MODES .............................................................................................. 9
7.1
Device Bus Operations ................................................................................................... 9
7.2
Auto-select Codes (High Voltage Method) ................................................................... 10
7.3
Embedded Programming Algorithm.............................................................................. 11
7.4
Embedded Erase Algorithm.......................................................................................... 12
7.5
Embedded #Data Polling Algorithm.............................................................................. 13
7.6
Embedded Toggle Bit Algorithm ................................................................................... 13
7.7
Software Product Identification and Boot Block Lockout Detection Acquisition Flow .. 14
7.8
Boot Block Lockout Enable Acquisition Flow................................................................ 15
DC CHARACTERISTICS .......................................................................................................... 16
8.1
Absolute Maximum Ratings .......................................................................................... 16
8.2
DC Operating Characteristics ....................................................................................... 16
8.3
Power-up Timing........................................................................................................... 17
Publication Release Date: April 19, 2005
Revision A7
-1-
W49F002U
9.
10.
CAPACITANCE......................................................................................................................... 17
AC CHARACTERISTICS .......................................................................................................... 17
10.1 AC Test Conditions....................................................................................................... 17
10.2 AC Test Load and Waveform ....................................................................................... 17
10.3 Read Cycle Timing Parameters.................................................................................... 18
10.4 Write Cycle Timing Parameters .................................................................................... 18
10.5 Datah Polling and Toggle Bit Timing Parameters......................................................... 19
10.6 Reset Timing Parameters ............................................................................................. 19
TIMING WAVEFORMS ............................................................................................................. 20
11.1 Read Cycle Timing Diagram......................................................................................... 20
11.2 #WE Controlled Command Write Cycle Timing Diagram ............................................. 20
11.3 #CE Controlled Command Write Cycle Timing Diagram.............................................. 21
11.4 Program Cycle Timing Diagram.................................................................................... 21
11.5 #DATA Polling Timing Diagram .................................................................................... 22
11.6 Toggle Bit Timing Diagram ........................................................................................... 22
11.7 Boot Block Lockout Enable Timing Diagram ................................................................ 23
11.8 Chip Erase Timing Diagram.......................................................................................... 23
11.9 Sector Erase Timing Diagram....................................................................................... 24
11.10 Reset Timing Diagram................................................................................................. 24
ORDERING INFORMATION..................................................................................................... 25
HOW TO READ THE TOP MARKING...................................................................................... 26
PACKAGE DIMENSIONS ......................................................................................................... 27
14.1 32-pin P-DIP ................................................................................................................. 27
14.2 32-pin PLCC ................................................................................................................. 27
14.3 32-pin STSOP (8 x 14 mm) .......................................................................................... 28
14.4 32-pin TSOP (8 x 20 mm)............................................................................................. 28
VERSION HISTORY ................................................................................................................. 29
11.
12.
13.
14.
15.
-2-
W49F002U
1. GENERAL DESCRIPTION
The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K
×
8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V
PP
is
not required. The unique cell architecture of the W49F002U results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory products).
The device can also be programmed and erased using standard EPROM programmers.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
Single 5-volt operations:
−
5-volt Read
−
5-volt Erase
−
5-volt Program
Fast Program operation:
−
Byte-by-Byte programming: 35
µS
(typ.)
Fast Erase operation: 100 mS (typ.)
Fast Read access time: 70/90/120 nS
Endurance: 10K cycles (typ.)
Ten-year data retention
Hardware data protection
One 16K byte Boot Block with Lockout
protection
Two 8K byte Parameter Blocks
Two Main Memory Blocks (96K, 128K) Bytes
Low power consumption
−
−
•
•
−
•
•
•
•
Active current: 25 mA (typ.)
Standby current: 20
µA
(typ.)
Automatic program and erase timing with
internal V
PP
generation
End of program or erase detection
−
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin DIP, 32-pin
STSOP (8 mm
×
14 mm), 32-pin TSOP
(8 mm
×
20 mm)
,
32-pin-PLCC
and 32-pin-PLCC Lead free
-3-
Publication Release Date: 8/10/2000
Revision A2.1
W49F002U
3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
VDD
#RESET
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
V
DD
#WE
A17
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
#CE
#OE
#WE
#RESET
CONTROL
OUTPUT
BUFFER
DQ0
.
.
DQ7
32-pin
DIP
26
25
24
23
22
21
20
19
18
17
A0
.
DECODER
.
BOOT BLOCK
16K BYTES
PARAMETER
BLOCK1
8K BYTES
PARAMETER
BLOCK2
8K BYTES
3FFFF
3C000
3BFFF
3A000
39FFF
A
1
2
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
A
1
5
3
A
1
6
2
#
R
E
S
E
T
V #
D W
D E
A
1
7
A17
1 32 31 30
29
28
27
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
32-pin
PLCC
38000
MAIN MEMORY 37FFF
BLOCK1
96K BYTES
20000
MAIN MEMORY 1FFFF
BLOCK2
128K BYTES
00000
26
25
24
23
22
21
14 15 16 17 18 19 20
D
Q
1
D
Q
2
V
s
s
D
Q
4
D
Q
5
D
Q
3
D
Q
6
5. PIN DESCRIPTION
A11
A9
A8
A13
A14
A17
#WE
V
DD
#RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
SYMBOL
PIN NAME
#RESET
A0
−
A17
DQ0
−
DQ7
#CE
#OE
#WE
V
DD
V
SS
Reset
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
32-pin
TSOP
A16
A15
A12
A7
A6
A5
A4
-4-
W49F002U
6. FUNCTIONAL DESCRIPTION
6.1 Device Operation
6.1.1 Read Mode
The read operation of the W49F002U is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is
de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the timing waveforms for details.
6.1.2 Write Mode
Device erase and program are accomplished via the command register. The content of the register
serves as inputs to the internal state machine. The state machine outputs dictate the function of the
device.
The command register itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information needed to execute the
command. The command register is written to bring #WE to logic low state when #CE is at logic low
state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,
whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens
first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing
parameters.
6.1.3 Standby Mode
There are two ways to implement the standby mode on the W49F002U device, both using the #CE pin.
A CMOS standby mode is achieved with the
#CE input held at V
DD
-0.3V. Under this condition the current is
typically reduced to less than 100
µA.
A TTL standby mode is achieved with the #CE pin held at V
IH
.
Under this condition the current is typically reduced to less than 3 mA.
In the standby mode the outputs are in the high impedance state, independent of the #OE input.
6.1.4 Output Disable Mode
With the #OE input at a logic high level (V
IH
), output from the device is disabled. This will cause the
output pins to be in a high impedance state.
6.1.5 Auto-select Mode
The auto-select mode allows the reading of a binary code from the device and will identify its
manufacturer and type. This mode is intended to be used by programming equipment for the purpose
of automatically matching the device to be programmed with its corresponding programming algorithm.
This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force V
ID
(11.5V to 12.5V) on address pin A9.
Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from V
IL
to
V
IH
. All addresses are don′t cares except A0 and A1 (see "Auto-select Codes").
Note: The hardware
SID read function is not included in all parts; please refer to Ordering Information for details.
The manufacturer and device codes may also be read via the command register; i.e., the W49F002U is
erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in "Auto-select Codes".
-5-
Publication Release Date: April 19, 2005
Revision A7
嵌入式系统
