W91820N SERIES
13-MEMORY TONE/PULSE DIALER WITH
HANDFREE, LOCK AND HOLD FUNCTIONS
GENERAL DESCRIPTION
The W91820N is a series of tone/pulse switchable telephone dialers with 13 memory, keytone, hold,
lock, and handfree dialing control features. These chips are fabricated using Winbond's high-
performance CMOS technology and thus offer good performance in low-voltage, low-power
operations.
FEATURES
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Tone/pulse switchable dialer
Two by 32 digits redial and save memory
Three by 32 digits one-touch direct repertory memory
Ten by 32 digits two-touch indirect repertory memory
Pulse-to-tone (*/T) keypad for long distance call operation
Chain dialing
Uses 5
×
5 keyboard
Easy operation with redial, flash, pause, and */T keypads
Pause, P→T (pulse-to-tone) can be stored as a digit in memory
Dialing rate:10 ppS or 20 ppS by mask option
Minimum tone output duration: 93 mS (unless W91824N/AN is 87 mS)
Minimum intertone pause: 93 mS (unless W91824N/AN is 87mS)
Pause time: 3.6 sec. (unless W91824N/AN is 2.0 sec.)
Flash break time (73 mS, 100 mS, 300 mS, or 600 mS) selectable by keypad; pause time is 1.0 S
Make/break ratio (2:3 or 1:2) selectable by MODE pin
Mute key for speech network mute
No key will be accepted except the "HOLD" key when in the Hold mode
Key tone output for valid keypad entry recognition
On-chip power-on reset
Uses 3.579545 MHz crystal or ceramic resonator
20, or 22-pin dual-in-line plastic package
The different dialers in the W91820N series are shown in the following table:
TYPE NO.
W91820N/824N
W91820AN/824AN
W91820LN
W91820ALN
W91822N
W91822AN
PULSE (ppS)
10
10
10
10
20
20
LOCK
-
-
√
√
-
-
KEY TONE
√
√
-
-
√
√
HANDFREE DIALING
-
√
-
√
-
√
PACKAGE (PINS)
20
22
20
22
20
22
Note: W91824N/824AN for French only.
-1-
Publication Release Date: May 1999
Revision A2
W91820N SERIES
PIN CONFIGURATIONS
C1
C1
C2
C3
C4
KT
H/P MUTE
V
SS
XT
XT
T/P MUTE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
R4
R3
R2
R1
N.C.
V
DD
MODE
DTMF
DP
HKS
C2
C3
C4
KT
H/P MUTE
V
SS
XT
XT
T/P MUTE
HFI
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
R4
R3
R2
R1
N.C.
V
DD
MODE
DTMF
DP
HKS
HFO
W91820N/822N
/824N
W91820AN/822AN
/824AN
C1
C1
C2
C3
C4
LOCK
H/P MUTE
V
SS
XT
XT
T/P MUTE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
R4
R3
R2
R1
N.C.
V
DD
MODE
DTMF
DP
HKS
C2
C3
C4
LOCK
H/P MUTE
V
SS
XT
XT
T/P MUTE
HFI
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
R4
R3
R2
R1
N.C.
V
DD
MODE
DTMF
DP
HKS
HFO
W91820LN
W91820ALN
-2-
W91820N SERIES
PIN DESCRIPTION
SYMBOL
Column-
Row
Inputs
20-PIN
1−4
&
17−20
22-PIN
1−4
&
19−22
I/O
I
FUNCTION
The keyboard input is compatible with a standard 5
×
5
keyboard, an inexpensive single contact (Form A) keyboard,
and electronic input.
In normal operation, any single button can be pushed to
produce dual tone, pulses, or functions. Activation of two or
more buttons will result in no response except for a single
tone.
XT
8
8
I
A built-in inverter together with an inexpensive 3.579545 MHz
crystal supplies the oscillator. The oscillator stops when there
is no keypad input. The crystal frequency deviation is 0.02%.
Crystal oscillator output pin.
The T/P MUTE is a conventional CMOS N-channel open
drain output.
The output transistor turns on with a low level during a dialing
sequence (both pulse and tone mode). Otherwise, it is off.
N.C.
MODE
16
14
18
16
-
I
No connect
Connecting the mode pin to V
SS
places the dialer in tone
mode.
Connecting the mode pin to V
DD
places the dialer in pulse
mode with an M/B ratio of 40:60.
Leaving the mode pin floating places the dialer in pulse mode
with an M/B ratio of 33.3:66.7.
HKS
11
13
I
The HKS (hook switch) input is used to sense whether the
handset is on-hook or off-hook.
In on-hook state, HKS = 1: chip is in sleeping mode, no
operation.
In off-hook state, HKS = 0: chip is enabled for normal
operation.
HKS pin is pulled to V
DD
by internal resistor.
KT
(W91820N/8
20AN/822N/
824N/822AN
/824AN only)
XT
T/P
MUTE
9
10
9
10
O
O
5
5
O
The key tone output is a conventional CMOS inverter. The
key tone is generated when any valid key is pressed; the KT
pin generates a 1.2 KHz square wave at 35 mS. When no key
is pressed, the KT pin remains in low state.
-3-
Publication Release Date: May 1999
Revision A2
W91820N SERIES
Pin Description, continued
SYMBOL
LOCK
(W91820LN/
820ALN only)
20-PIN
5
22-PIN
5
I/O
I
FUNCTION
The function of this terminal is to prevent "0" dialing and "9"
dialing under PABX system long distance call control. When
the first key input after reset is 0 or 9, all key inputs,
including the 0 or 9 key, become invalid and the chip
generates no output. The telephone is reinitialized by a
reset.
The function of the LOCK pin is shown below:
LOCK PIN
V
DD
Floating
V
SS
FUNCTION
"0", "9" dialing inhibited
Normal dialing Mode
"0" dialing inhibited
H/P MUTE
6
6
I
The H/P MUTE is a conventional inverter output. During
pulse dialing, flash break or hold period, this output is active
high; otherwise, it remains in low state.
N-channel open drain dialing pulse output.
Flash key will cause DP to be active in either tone mode or
pulse mode.
In lock mode, the DP remains low for 300 mS durint off-
hook delay time.
The timing diagram for pulse mode is shown in Figure 1(a,
b).
DP
12
14
O
DTMF
13
15
O
During pulse dialing, this pin remains in a low state
regardless of the keypad input. In tone mode, it will output a
dual or single tone.
A detailed timing diagram for tone mode is shown in Figure
2(a, b).
OUTPUT FREQUENCY
Specified
R1
R2
R3
R4
C1
C2
C3
697
770
852
941
1209
1336
1477
Actual
699
766
848
948
1216
1332
1472
Error %
+0.28
-0.52
-0.47
+0.74
+0.57
-0.30
-0.34
V
DD
, V
SS
15, 7
17, 7
I
Power input pins for the dialer chip. V
DD
is the power and
V
SS
is the ground.
-4-
W91820N SERIES
Pin Description, continued
SYMBOL
HFI , HFO
20-PIN
-
22-PIN
11, 12
I/O
I, O Handfree control pins.
FUNCTION
A low pulse on the HFI input pin toggles the handfree
control state. The status of the handfree control state is
listed in the following table:
CURRENT STATE
HOOK SW.
-
On Hook
Off Hook
On Hook
Off Hook
Off Hook
HFO
Low
High
High
-
Low
High
INPUT
HFI
HFI
HFI
Off Hook
On Hook
On Hook
NEXT STATE
HFO
High
Low
Low
Low
Low
High
DIALING
Yes
No
Yes
Yes
No
Yes
The HFI pin is pulled to V
DD
by an internal resistor.
A detailed timing diagram is shown in Figure 3.
BLOCK DIAGRAM
XT
XT
HKS
HFI
SYSTEM CLOCK
GENERATOR
ROW
(R1 ~ R4, Vx/R5)
KEYBOARD
INTERFACE
COLUMN
(C1 ~ C4, Vss)
LOCATION
LATCH
READ/WRITE
COUNTER
CONTROL
LOGIC
LOCK
MODE
RAM
PULSE
CONTROL
LOGIC
T/P MUTE
KT
DP
HFO
H/P MUTE
DTMF
D/A
CONVERTER
ROW & COLUMN
PROGRAMMABLE
COUNTER
DATA LATCH
& DECODER
-5-
Publication Release Date: May 1999
Revision A2
