PRELIMINARY W986432DH
512K
×
4 BANKS
×
32 BITS SDRAM
GENERAL DESCRIPTION
W986432DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words
×
4 banks
×
32 bits. Using pipelined architecture and 0.175
µm
process technology,
W986432DH delivers a data bandwidth of up to 800M bytes per second (5). For different application,
W986432DH is sorted into four speed grades: -5, -55, -6, -7,-8.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W986432DH is ideal for main memory in
high performance applications.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V ±0.3V power supply
524288 words
×
4 banks
×
32 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Sequential and Interleave burst
Burst read, single write operation
Byte data controlled by DQM
Power-down Mode
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in 86-pin TSOP II, 400 mil - 0.50
-1-
Publication Release Date: May 2000
Revision A0
PRELIMINARY W986432DH
512K
×
4 BANKS
×
32 BITS SDRAM
PIN CONFIGURATION
DQM1
DQM3
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
45
42
DQ23
V
CC
Q
V
CC
Q
V
CC
Q
V
CC
Q
V
SS
Q
V
SS
Q
V
SS
Q
V
SS
Q
CKE
DQ9
DQ8
CLK
V
SS
V
SS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
A10/AP
VSSQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQM0
DQM2
V
CC
Q
V
CC
Q
DQ22
CAS
RAS
BS0
VCC
VCC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
BS1
WE
NC
CS
NC
V
SS
Q
NC
A0
A1
A2
V
SS
Q
V
SS
Q
V
CC
Q
V
CC
PIN DESCRIPTION
PIN NAME
A0−A10
FUNCTION
Address
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
A10 is sampled during a precharge command to determine if
all banks are to be precharged or bank selected by BS0, BS1.
BS0, BS1
DQ0−DQ31
CS
Bank Select
Data Input/
Output
Chip Select
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the
clock
RAS
,
CAS
and
WE
define the operation to be
executed.
Referred to
RAS
Referred to
RAS
RAS
Row Address
Strobe
Column Address
Strobe
Write Enable
CAS
WE
-2-
Publication Release Date: May 2000
Revision A0
V
CC
Q
V
CC
43
2
3
4
5
6
7
8
1
9
44
V
SS
NC
NC
NC
NC
V
ss
A9
A8
A7
A6
A5
A4
A3
W986432DH
DQM0−
DQM3
CLK
CKE
Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency.
Clock Inputs
Clock Enable
System clock used to sample inputs on the rising edge of
clock.
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
V
CC
V
SS
V
CCQ
V
SSQ
NC
Power (+3.3V)
Ground
Power (+3.3V) for Separated power from V
CC
, to improve DQ noise immunity.
I/O buffer
Ground for I/O
buffer
No Connection
Separated ground from V
SS
, to improve DQ noise immunity.
No connection
-3-
Publication Release Date: May 2000
Revision A0
W986432DH
BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
CAS
GENERATOR
COMMAND
DECODER
WE
ROW DECODER
COLUMN DECODER
COLUMN DECODER
ROW DECODER
A10
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A0
ADDRESS
BUFFER
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
A9
BS0
BS1
DATA CONTROL
CIRCUIT
COLUMN
COUNTER
DQ
BUFFER
DQ0
DQ31
REFRESH
COUNTER
DQM0~3
COLUMN DECODER
ROW DECODER
ROW DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 2048 * 256 * 32
-4-
W986432DH
DC CHARACTERISTICS
Absolute Maximum Rating
PARAMETER
Input, Column Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
SYM.
V
IN
, V
OUT
V
CC,
V
CCQ
T
OPR
T
STG
T
SOLDER
P
D
I
OUT
RATING
-0.3
−
V
CC
+0.3
-0.3
−
4.6
0
−
70
-55
−
150
260
1
50
UNIT
V
V
°C
°C
°C
W
mA
NOTES
1
1
1
1
1
1
1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to 70°C)
PARAMETER
Power Supply Voltage
Power Supply Voltage (for I/O
Buffer)
Input High Voltage
Input Low Voltage
SYM.
V
CC
V
CCQ
V
IH
V
IL
MIN.
3.0
3.0
2.0
-0.3
TYP.
3.3
3.3
-
-
MAX.
3.6
3.6
V
CC
+0.3
0.8
UNIT
V
V
V
V
NOTE
S
2
2
2
2
Note: V
IH
(max.) = V
CC
/V
CC
Q+1.2V for pulse width < 5 nS
V
IL
(min.) = V
SS
/V
SS
Q-1.2V for pulse width < 5 nS
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°C,
f = 1 MHz)
PARAMETER
Input Capacitance
(A0 to A11, BS0, BS1,
CS
SYM.
C
i
MIN.
2.5
MAX.
4
UNIT
pf
,
RAS
,
CAS
,
WE
,
DQM, CKE)
C
CLK
C
o
2.5
4
4
6.5
pf
pf
Input Capacitance (CLK)
Input/Output capacitance (DQ0−DQ31)
Note: These parameters are periodically sampled and not 100% tested
-5-
Publication Release Date: May 2000
Revision A0
