W9864G2JH
512K
4 BANKS
32BITS SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
ORDER INFORMATION ............................................................................................................. 3
PIN CONFIGURATION ............................................................................................................... 4
PIN DESCRIPTION ..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION.................................................................................................... 7
7.1
Power Up and Initialization ............................................................................................. 7
7.2
Programming Mode Register .......................................................................................... 7
7.3
Bank Activate Command ................................................................................................ 7
7.4
Read and Write Access Modes ...................................................................................... 7
7.5
Burst Read Command .................................................................................................... 8
7.6
Burst Command .............................................................................................................. 8
7.7
Read Interrupted by a Read ........................................................................................... 8
7.8
Read Interrupted by a Write ............................................................................................ 8
7.9
Write Interrupted by a Write ............................................................................................ 8
7.10 Write Interrupted by a Read ............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode .................................................................... 9
7.13 Addressing Sequence of Interleave Mode ...................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command .................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode........................................................................................................ 11
7.18 No Operation Command ............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode .................................................................................................... 11
OPERATION MODE ................................................................................................................. 12
8.1
Simplified Stated Diagram ............................................................................................ 13
ELECTRICAL CHARACTERISTICS ......................................................................................... 14
9.1
Absolute Maximum Ratings .......................................................................................... 14
9.2
Recommended DC Operating Conditions .................................................................... 14
9.3
Capacitance .................................................................................................................. 15
9.4
DC Characteristics ........................................................................................................ 15
9.5
AC Characteristics and Operating Condition ................................................................ 16
TIMING WAVEFORMS ............................................................................................................. 18
10.1 Command Input Timing ................................................................................................ 18
10.2 Read Timing.................................................................................................................. 19
10.3 Control Timing of Input/Output Data ............................................................................. 20
10.4 Mode Register Set Cycle .............................................................................................. 21
Publication Release Date: Mar. 13, 2017
Revision: A03
-1-
8.
9.
10.
W9864G2JH
11.
OPERATING TIMING EXAMPLE ............................................................................................. 22
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ...................................... 22
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ........... 23
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ...................................... 24
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ........... 25
11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 26
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 27
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 28
11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 29
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 30
11.10 Auto-precharge Write (Burst Length = 4) .................................................................... 31
11.11 Auto Refresh Cycle ..................................................................................................... 32
11.12 Self Refresh Cycle ....................................................................................................... 33
11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................. 34
11.14 Power Down Mode ...................................................................................................... 35
11.15 Auto-precharge Timing (Write Cycle) .......................................................................... 36
11.16 Auto-precharge Timing (Read Cycle) .......................................................................... 37
11.17 Timing Chart of Read to Write Cycle ........................................................................... 38
11.18 Timing Chart of Write to Read Cycle ........................................................................... 38
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) .......................................... 39
11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39
11.21 CKE/DQM Input Timing (Write Cycle) ......................................................................... 40
11.22 CKE/DQM Input Timing (Read Cycle) ......................................................................... 41
11.23 Power Up and Initialization .......................................................................................... 42
PACKAGE SPECIFICATION .................................................................................................... 43
REVISION HISTORY ................................................................................................................ 44
12.
13.
Publication Release Date: Mar. 13, 2017
Revision: A03
-2-
W9864G2JH
1. GENERAL DESCRIPTION
W9864G2JH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words
4 banks
32 bits. W9864G2JH delivers a data bandwidth of up to 200M words per
second. For different application, The W9864G2JH is sorted into the following speed grades: -5, -6, -6I
and -7. The -5 parts can run up to 200MHz/CL3. The -6 and -6I parts can run up to 166 MHz/CL3, -6I
industrial grade which is guaranteed to support -40°C ≤ T
A
≤ 85°C. The -7 parts can run up to 143
MHz/CL3.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed
at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command.
Column addresses are automatically generated by the SDRAM internal counter in burst operation.
Random column read is also possible by providing its address at each clock cycle. The multiple bank
nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9864G2JH is ideal for main memory in
high performance applications.
2. FEATURES
3.3V ± 0.3V for -5/-6/-6I grades power supply
2.7V
~
3.6V for -7 grade power supply
Up to 200 MHz Clock Frequency
524,288 words 4 banks
32 bits organization
Self Refresh Current: Standard and Low Power
CAS Latency: 2 & 3
Burst Length: 1, 2, 4, 8 and full page
Sequential and Interleave Burst
Byte data controlled by DQM0-3
Auto-precharge and controlled precharge
Burst read, single write operation
4K Refresh cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 86-pin, using Lead free materials with RoHS compliant
3. ORDER INFORMATION
PART NUMBER
SPEED
MAXIMUM SELF
REFRESH CURRENT
OPERATING
TEMPERATURE
W9864G2JH-5
W9864G2JH-6
W9864G2JH-6I
W9864G2JH-7
200MHz/CL3
166MHz/CL3
166MHz/CL3
143MHz/CL3
2mA
2mA
2mA
2mA
0°C ~ 70°C
0°C ~ 70°C
-40°C ~ 85°C
0°C ~ 70°C
Publication Release Date: Mar. 13, 2017
Revision: A03
-3-
W9864G2JH
4. PIN CONFIGURATION
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
NC
V
DD
DQM0
WE
CAS
RAS
CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SSQ
DQ17
DQ18
V
DDQ
DQ19
DQ20
V
SSQ
DQ21
DQ22
V
DDQ
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DDQ
DQ30
DQ29
V
SSQ
DQ28
DQ27
V
DDQ
DQ26
DQ25
V
SSQ
DQ24
V
SS
Publication Release Date: Mar. 13, 2017
Revision: A03
-4-
W9864G2JH
5. PIN DESCRIPTION
PIN NUMBER
24, 25, 26, 27, 60, 61, 62,
63, 64, 65, 66
PIN NAME
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0A10. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or
bank selected by BS0, BS1.
Select bank to activate during row address latch
time, or bank to read/write during address latch
time.
A0A10
Address
22, 23
2, 4, 5, 7, 8, 10, 11, 13, 31,
33, 34, 36, 37, 39, 40, 42,
45, 47, 48, 50, 51, 53, 54,
56, 74, 76, 77, 79, 80, 82,
83, 85
20
BS0, BS1
Bank Select
DQ0DQ31
Data
Input/ Output
Multiplexed pins for data output and input.
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising
edge of the clock
RAS
,
CAS
and
WE
define
the operation to be executed.
19
RAS
Row Address
Strobe
18
17
CAS
Column Address
Referred to
RAS
Strobe
Write Enable
Input/Output
Mask
Referred to
RAS
The output buffer is placed at Hi-Z (with latency
of 2) when DQM is sampled high in read cycle.
In write cycle, sampling DQM high will block the
write operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and
deactivation. When CKE is low, Power Down
mode, Suspend mode, or Self Refresh mode is
entered.
Power for input buffers and logic circuit inside
DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Separated power from VDD, to improve DQ
noise immunity.
WE
DQM0DQM3
16, 28, 59, 71
68
CLK
Clock Inputs
67
CKE
Clock Enable
1, 15, 29, 43
44, 58, 72, 86
3, 9, 35, 41, 49, 55, 75, 81
6, 12, 32, 38, 46, 52, 78, 84
14, 21, 30, 57, 69, 70, 73
V
DD
V
SS
V
DDQ
V
SSQ
NC
Power
Ground
Power for I/O
Buffer
Ground for I/O Separated ground from VSS, to improve DQ
Buffer
noise immunity.
No Connection No connection.
Publication Release Date: Mar. 13, 2017
Revision: A03
-5-
