W989D6CB / W989D2CB
512Mb Mobile LPSDR
TABLE OF CONTENTS
1. GENERAL DESCRIPTION .......................................................................................................... 3
2. FEATURES .................................................................................................................................. 3
3. PIN CONFIGURATION ................................................................................................................ 4
3.1 Ball Assignment: LPSDR X 16 ............................................................................................................ 4
3.2 Ball Assignment: LPSDR X 32 ............................................................................................................ 4
4. PIN DESCRIPTION...................................................................................................................... 5
4.1 Signal Description ............................................................................................................................... 5
4.2 Addressing Table ................................................................................................................................ 5
5. BLOCK DIAGRAM ...................................................................................................................... 6
6. ELECTRICAL CHARACTERISTICS ........................................................................................... 7
6.1 Absolute Maximum Ratings ................................................................................................................ 7
6.2 Operating Conditions .......................................................................................................................... 7
6.3 Capacitance ........................................................................................................................................ 7
6.4 DC Characteristics .............................................................................................................................. 8
6.5 Automatic Temperature Compensated Self Refresh Current Feature .............................................. 10
6.6 AC Characteristics And AC Operating Conditions ............................................................................ 11
6.6.1 AC Characteristics.................................................................................................................................... 11
6.6.2 AC Test Condition .................................................................................................................................... 12
6.6.3 AC Latency Characteristics ...................................................................................................................... 13
7. FUNCTION DESCRIPTION ....................................................................................................... 14
7.1 Command Function ........................................................................................................................... 14
7.1.1Table 1. Truth Table .................................................................................................................................. 14
7.1.2 Functional Truth Table ............................................................................................................................. 15
7.1.3 Function Truth Table for CKE .................................................................................................................. 18
7.1.4 Bank Activate Command .......................................................................................................................... 19
7.1.5 Bank Precharge Command ...................................................................................................................... 19
7.1.6 Precharge All Command .......................................................................................................................... 19
7.1.7 Write Command ....................................................................................................................................... 19
7.1.8 Write with Auto Precharge Command ...................................................................................................... 19
7.1.9 Read Command ....................................................................................................................................... 19
7.1.10 Read with Auto Precharge Command.................................................................................................... 19
7.1.11 Extended Mode Register Set Command ............................................................................................... 19
7.1.12 Mode Register Set Command ................................................................................................................ 20
7.1.13 No-Operation Command ........................................................................................................................ 20
7.1.14 Burst Stop Command ............................................................................................................................. 20
7.1.15 Device Deselect Command.................................................................................................................... 20
7.1.16 Auto Refresh Command ......................................................................................................................... 20
7.1.17 Self Refresh Entry Command ................................................................................................................ 20
7.1.18 Self Refresh Exit Command ................................................................................................................... 20
7.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command ......................................................... 20
7.1.20 Clock Suspend Mode Exit / Power Down Mode Exit Command ............................................................ 20
7.1.21 Data Write/Output Enable, Data Mask/Output Disable Command ........................................................ 21
8.OPERATION ............................................................................................................................... 21
8.1 Read Operation ................................................................................................................................. 21
8.2 Write Operation ................................................................................................................................. 21
8.3 Precharge ......................................................................................................................................... 22
8.3.1 Auto Precharge ........................................................................................................................................ 22
8.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge) ............................. 22
8.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge) ............................ 23
8.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge) ............................ 24
8.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) .......................... 25
- 1-
Publication Release Date: Sep, 22, 2011
Revision A01-005
W989D6CB / W989D2CB
512Mb Mobile LPSDR
8.4 Burst Termination .............................................................................................................................. 26
8.5 Mode Register Operation .................................................................................................................. 27
8.5.1 Burst Length field (A2~A0) ....................................................................................................................... 27
8.5.2 Addressing Mode Select (A3) .................................................................................................................. 27
8.5.3 Addressing Sequence for Sequential Mode ............................................................................................. 28
8.5.4 Addressing Sequence for Interleave Mode .............................................................................................. 28
8.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13) .......................................... 29
8.5.6 Read Cycle
CAS
Latency = 3 ................................................................................................................ 29
8.5.7
CAS
Latency field (A6~A4) ................................................................................................................... 30
8.5.8 Mode Register Definition .......................................................................................................................... 30
8.6 Extended Mode Register Description................................................................................................ 31
8.7 Simplified State Diagram................................................................................................................... 32
9. CONTROL TIMING WAVEFORMS ........................................................................................... 33
9.1 Command Input Timing ..................................................................................................................... 33
9.2 Read Timing ...................................................................................................................................... 34
9.3 Control Timing of Input Data (x16) .................................................................................................... 35
9.4 Control Timing of Output Data (x16) ................................................................................................. 36
9.5 Control Timing of Input Data (x32) .................................................................................................... 37
9.6 Control Timing of Output Data (x32) ................................................................................................. 38
9.7 Mode register Set (MRS) Cycle ........................................................................................................ 39
9.8 Extended Mode register Set (EMRS) Cycle ...................................................................................... 40
10. OPERATING TIMING EXAMPLE ............................................................................................ 41
10.1 Interleaved Bank Read (Burst Length = 4,
CAS
Latency = 3)....................................................... 41
10.2 Interleaved Bank Read (Burst Length = 4,
CAS
Latency = 3, Auto Precharge)............................ 42
10.3 Interleaved Bank Read (Burst Length = 8,
CAS
Latency = 3)....................................................... 43
10.4 Interleaved Bank Read (Burst Length = 8,
CAS
Latency = 3, Auto Precharge)............................ 44
10.5 Interleaved Bank Write (Burst Length = 8) ...................................................................................... 45
10.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ........................................................... 46
10.7 Page Mode Read (Burst Length = 4,
CAS
Latency = 3) ............................................................... 47
10.8 Page Mode Read / Write (Burst Length = 8,
CAS
Latency = 3) .................................................... 48
10.9 Auto Precharge Read (Burst Length = 4,
CAS
Latency = 3)......................................................... 49
10.10 Auto Precharge Write (Burst Length = 4) ...................................................................................... 50
10.11 Auto Refresh Cycle ....................................................................................................................... 51
10.12 Self Refresh Cycle ........................................................................................................................ 52
10.13 Power Down Mode ........................................................................................................................ 53
10.14 Burst Read and Single Write (Burst Length = 4,
CAS
Latency = 3) ............................................ 54
10.15 Deep Power Down Mode Entry ..................................................................................................... 55
10.16 Deep Power Down Mode Exit ....................................................................................................... 56
10.17 Auto Precharge Timing (Read Cycle) ........................................................................................... 57
10.18 Auto Precharge Timing (Write Cycle)............................................................................................ 58
10.19 Timing Chart of Read to Write Cycle............................................................................................. 59
10.20 Timing Chart for Write to Read Cycle ........................................................................................... 59
10.21 Timing Chart for Burst Stop Cycle (Burst Stop Command) ........................................................... 60
10.22 Timing Chart for Burst Stop Cycle (Precharge Command) ........................................................... 60
10.23 CKE/DQM Input Timing (Write Cycle) ........................................................................................... 61
10.24 CKE/DQM Input Timing (Read Cycle)........................................................................................... 62
11. PACKAGE DIMENSION .......................................................................................................... 63
11.1 : LPSDR X 16 .................................................................................................................................. 63
11.2 : LPSDR X 32 .................................................................................................................................. 64
12.ORDERING INFORMATION .................................................................................................... 65
13. REVISION HISTORY ............................................................................................................... 66
- 2-
Publication Release Date: Sep, 22, 2011
Revision A01-005
W989D6CB / W989D2CB
512Mb Mobile LPSDR
1. GENERAL DESCRIPTION
The Winbond 512Mb Low Power SDRAM is a low power synchronous memory containing 536,870,912 memory cells
fabricated with Winbond high performance process technology.
It is designed to consume less power than the ordinary SDRAM with low power features essential for applications which
use batteries. It is available in two organizations: 4,194,304-words × 4 banks × 32 bits or 8,388,608 words × 4 banks × 16
bits. The device operates in a fully synchronous mode, and the output data are synchronized to positive edges of the
system clock and is capable of delivering data at clock rate up to 166MHz. The device supports special low power functions
such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR).
The Low Power SDRAM is suitable for 2.5G / 3G cellular phone, PDA, digital still camera, mobile game consoles and other
handheld applications where large memory density and low power consumption are required. The device operates from
1.8V power supply, and supports the 1.8V LVCMOS bus interface.
2. FEATURES
Power supply V
DD
= 1.7V~1.95V
V
DDQ
= 1.7V~1.95V
Frequency : 166MHz(-6),133MHz(-75)
Programmable Partial Array Self Refresh
Power Down Mode
Deep Power Down Mode (DPD)
Programmable output buffer driver strength
Automatic Temperature Compensated Self Refresh
CAS
Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Refresh: 8K refresh cycle / 64ms
Interface: LVCMOS
Support package :
54 balls VFBGA (x16)
90 balls VFBGA (x32)
Operating Temperature Range
Extended (-25°C ~ +85°C)
Industrial (-40°C ~ +85°C)
- 3-
Publication Release Date: Sep, 22, 2011
Revision A01-005
W989D6CB / W989D2CB
512Mb Mobile LPSDR
3. PIN CONFIGURATION
3.1 Ball Assignment: LPSDR X 16
54Ball FBGA
1
A
B
C
D
E
F
G
H
J
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
VSS
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
4 5 6
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
8
DQ0
DQ2
DQ4
DQ6
LDQM
9
VDD
DQ1
DQ3
DQ5
DQ7
CAS
BA0
A0
A3
RAS
BA1
A1
A2
WE
CS
A10
VDD
(Top View) Pin Configuration
3.2 Ball Assignment: LPSDR X 32
90Ball FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
2
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
3
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
A12
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
4 5 6
7
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
8
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
9
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
CS
RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
CAS
VDD
DQ6
DQ1
VDDQ
VDD
WE
DQ7
DQ5
DQ3
VSSQ
DQ0
(Top View) Pin Configuration
- 4-
Publication Release Date: Sep, 22, 2011
Revision A01-005
W989D6CB / W989D2CB
512Mb Mobile LPSDR
4. PIN DESCRIPTION
4.1 Signal Description
BALL NAME
A [n : 0]
BA0, BA1
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
FUNCTION
Address
Bank Select
DESCRIPTION
Multiplexed pins for row and column address.
A10 is Auto Precharge Select
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
Data Input/ Output Multiplexed pins for data output and input.
Chip Select
Row
Address Strobe
Column
Address Strobe
Write Enable
I/O Mask
Clock Inputs
Clock Enable
Power
Ground
Power for I/O
Buffer
Ground for
I/O Buffer
No Connection
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the clock,
RAS
,
CAS
and
WE
define the operation to be executed.
Referred to
RAS
Referred to
WE
The output buffer is placed at Hi-Z (with latency of 2 in CL=2, 3;)
when DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency.
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is
low, Power Down mode, Suspend mode or Self Refresh mode is
entered.
Power supply for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Power supply separated from VDD, used for output buffers to
improve noise.
Separated ground from VSS, used for output buffers to improve
noise.
No connection
CS
RAS
CAS
WE
UDQM / LDQM(x16)
DQM0 ~ DQM3 (x32)
CLK
CKE
VDD
VSS
VDDQ
VSSQ
NC
4.2 Addressing Table
ITEM
Number of banks
Bank address pins
Auto precharge pin
Row addresses
X16
Column addresses
Refresh count
Row addresses
x32
Column addresses
Refresh count
512 Mb
4
BA0,BA1
A10/AP
A0-A12
A0-A9
8K
A0-A12
A0-A8
8K
- 5-
Publication Release Date: Sep, 22, 2011
Revision A01-005
