White Electronic Designs
WV3HG2128M64EEU-D4
ADVANCED*
2GB – 2x128Mx64 DDR2 SDRAM UNBUFFERED
FEATURES
200-pin, dual in-line memory module (SO-DIMM)
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
V
CC
= 1.8V ±0.1V
V
CCSPD
= 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Dual Rank
RoHS compliant
JEDEC Package option
• 200 Pin (SO-DIMM)
• PCB – 30.00mm (1.181") TYP.
DESCRIPTION
The WV3HG2128M64EEU is a 2x128Mx64 Double Data
Rate DDR2 SDRAM high density SO-DIMM. This memory
module consists of sixteen 128Mx8 bit with 8 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
PC2-3200
Clock Speed
CL-t
RCD
-t
RP
* Consult factory for availability
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
200MHz
3-3-3
October 2006
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
51
DQS2
101
A1
151
DQ42
1
V
REF
2
V
SS
52
DM2
102
A0
152
DQ46
53
V
SS
103
V
CC
153
DQ43
3
V
SS
4
DQ4
54
V
SS
104
V
CC
154
DQ47
5
DQ0
55
DQ18
105
A10/AP
155
V
SS
6
DQ5
56
DQ22
106
BA1
156
V
SS
7
DQ1
57
DQ19
107
BA0
157
DQ48
8
V
SS
58
DQ23
108
RAS#
158
DQ52
9
V
SS
59
V
SS
109
WE#
159
DQ49
10
DM0
60
V
SS
110
CS0#
160
DQ53
11
DQS0#
61
DQ24
111
V
CC
161
V
SS
12
V
SS
62
DQ28
112
V
CC
162
V
SS
13
DQS0
63
DQ25
113
CAS#
163
NC
14
DQ6
64
DQ29
114
ODT0
164
CK1
65
V
SS
115
CS1#
165
V
SS
15
V
SS
16
DQ7
66
V
SS
116
A13
166
CK1#
17
DQ2
67
DM3
117
V
CC
167
DQS6#
18
V
SS
68
DQS3#
118
V
CC
168
V
SS
19
DQ3
69
NC
119
ODT1
169
DQS6
20
DQ12
70
DQS3
120
NC
170
DM6
21
V
SS
71
V
SS
121
V
SS
171
V
SS
22
DQ13
72
V
SS
122
V
SS
172
V
SS
23
DQ8
73
DQ26
123
DQ32
173
DQ50
74
DQ30
124
DQ36
174
DQ54
24
V
SS
25
DQ9
75
DQ27
125
DQ33
175
DQ51
26
DM1
76
DQ31
126
DQ37
176
DQ55
27
V
SS
77
V
SS
127
V
SS
177
V
SS
28
V
SS
78
V
SS
128
V
SS
178
V
SS
29
DQS1#
79
CKE0
129
DQS4#
179
DQ56
30
CK0
80
CKE1
130
DM4
180
DQ60
31
DQS1
81
V
CC
131
DQS4
181
DQ57
32
CK0#
82
V
CC
132
V
SS
182
DQ61
83
NC
133
V
SS
183
V
SS
33
V
SS
34
V
SS
84
NC
134
DQ38
184
V
SS
35
DQ10
85
BA2
135
DQ34
185
DM7
36
DQ14
86
NC
136
DQ39
186
DQS7#
37
DQ11
87
V
CC
137
DQ35
187
V
SS
38
DQ15
88
V
CC
138
V
SS
188
DQS7
39
V
SS
89
A12
139
V
SS
189
DQ58
40
V
SS
90
A11
140
DQ44
190
V
SS
41
V
SS
91
A9
141
DQ40
191
DQ59
42
V
SS
92
A7
142
DQ45
192
DQ62
43
DQ16
93
A8
143
DQ41
193
V
SS
44
DQ20
94
A6
144
V
SS
194
DQ63
45
DQ17
95
V
CC
145
V
SS
195
SDA
46
DQ21
96
V
CC
146
DQS5#
196
V
SS
47
V
SS
97
A5
147
DM5
197
SCL
48
V
SS
98
A4
148
DQS5
198
SA0
49
DQS2#
99
A3
149
V
SS
199
V
CCSPD
50
NC
100
A2
150
V
SS
200
SA1
WV3HG2128M64EEU-D4
ADVANCED
PIN NAMES
Pin Name
CK0,CK1
CK0#, CK1#
CKE0, CKE1
RAS#
CAS#
WE#
CS0#, CS1#
A0-A13
A10/AP
BA0 - BA2
ODT0,ODT1
SCL
SDA
SA0, SA1
DQ0-DQ63
DM0-DM7
DQS0-DQS7
DQS0#-DQS7#
V
CC
V
SS
V
REF
V
CC
SPD
NC
Function
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Auto precharge
SDRAM Bank Address
On-die termination control
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
SPD address
Data Input/Output
Data Masks
Data strobes
Data strobes complement
Core and I/O Power
Ground
Input/Output Reference
SPD Power
Spare pins, No connect
October 2006
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG2128M64EEU-D4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
10 ohm + 5%
CKE1
ODT1
CS1#
CKE0
ODT0
CS0#
DQS0
DQS0#
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
CS0# O
D
DQS#
T
DM
0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
0
DQS
CS1# O
D
DQS#
T
DM
1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
1
DQS4
DQS4#
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
CS0# O
D
DQS#
T
DM
0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
0
DQS
CS1# O
D
DQS#
T
DM
1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
1
DQS1
DQS1#
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
CS0# O
DQS#
D
DM
T
0
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
0
DQS
CS1# O
DQS#
D
DM
T
1
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
1
DQS5
DQS5#
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
CS0# O
DQS#
D
DM
T
0
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
0
DQS
CS1# O
DQS#
D
DM
T
1
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
1
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
CS0# O
D
DQS#
T
DM
0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
0
DQS
CS1# O
D
DQS#
T
DM
1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
1
DQS6
DQS6#
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS
CS0# O
D
DQS#
T
DM
0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
0
DQS
CS1# O
D
DQS#
T
DM
1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
C
K
E
1
DQS3
DQS3#
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
CS0# O
D
DQS#
T
DM
0
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
0
DQS
CS1# O
D
DQS#
T
DM
1
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
1
DQS7
DQS7#
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
CS0# O
D
DQS#
T
DM
0
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
0
DQS
CS1# O
D
DQS#
T
DM
1
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
C
K
E
1
10 ohm ± 5%
BA0 - BA2
A0 - A13
RAS#
CAS#
WE#
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
SCL
SA0
SA1
SCL
A0
SPD
A1
A2
WP
* Clock Wiring
Clock Input
SDA
DDR2 SDRAMs
8 DDR2 SDRAMs
8 DDR2 SDRAMs
*CK0/CK0#
*CK1/CK1#
* Wire per Clock Loading
Table/Wiring Diagrams
V
CC
SPD
V
REF
V
CC
V
SS
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs, V
CC,
V
CCQ
and V
CCL
DDR2 SDRAMs, SPD
Notes :
1. All resistor values are 22 ohms ± 5% unless otherwise specified
2. BAx, Ax, RAS#, CAS#, WE# resistors : 3.0 Ohms ±5%.
October 2006
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
All voltages referenced to V
SS
Rating
Parameter
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
Symbol
V
CC
V
REF
V
TT
Min.
1.7
0.49 x V
CC
V
REF
-0.04
Type
1.8
0.50 x V
CC
V
REF
WV3HG2128M64EEU-D4
ADVANCED
DC OPERATING CONDITIONS
Max.
1.9
0.51 x V
CC
V
REF
+0.04
Units
V
V
V
Notes
1
2
Notes:
1. V
REF
is expected to equal V
CC/2
of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V
REF
may not exceed +/-1 percent of the DC
value. Peak-to-peak AC noise on V
REF
may not exceed +/-2 percent of V
REF
. This measurment is to be taken at the nearest V
REF
bypass capacitor.
2. V
TT
in sot applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
IN
, V
OUT
T
STG
Parameter
Voltage on V
CC
pin relative to V
SS
Voltage on any pin relative to V
SS
Storage Temperature
Command/Address,
RAS#, CAS#, WE#
I
L
Input leakage current; Any input 0V<V
IN
<V
CC
; V
REF
input
0V<V
IN
<0.95V; Other pins not under test = 0V
CS#, CKE
CK, CK#
DM
I
OZ
I
VREF
Output leakage current; 0V<V
IN
<V
CC
; DQs and ODT are
disable
V
REF
leakage current; V
REF
= Valid V
REF
level
DQ, DQS, DQS#
Min
-1.0
-0.5
-55
-80
-40
-40
-10
-10
-32
Max
2.3
2.3
100
80
40
40
10
10
32
Units
V
V
˚C
µA
µA
µA
µA
µA
µA
INPUT/OUTPUT CAPACITANCE
T
A
= 25°C, f = 100MHz
Parameter
Input Capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1), (ODT0, ODT1)
Input Capacitance (CS0#, CS1#)
Input Capacitance (CK0, CK0#, CK1, CK1#)
Input Capacitance (DM0 ~ DM7), (DQS0 ~ DQS7)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
(667)*
C
IN5
(533 & 400)
C
OUT1
(667)*
Input Capacitance (DQ0 ~ DQ63)
* 800Mb/s = TBD
October 2006
Rev. 1
Min
20
12
12
12
9
9
9
9
Max
36
20
20
20
11
12
11
12
Units
pF
pF
pF
pF
pF
pF
pF
pF
C
OUT1
(533 & 400)
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
Parameter
Operating temperature
Symbol
TOPER
WV3HG2128M64EEU-D4
ADVANCED
OPERATING TEMPERATURE CONDITION
Rating
0
°
to 85°
Units
°C
Notes
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Symbol
V
IH
(DC)
V
IL
(DC)
Min
V
REF
+ 0.125
-0.300
Max
V
CC
+ 0.300
V
REF
- 0.125
Units
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Input High (Logic 1) Voltage DDR2-400 & DDR2-533
Input Low (Logic 1) Voltage DDR2-667
Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
Input Low (Logic 0) Voltage DDR2-667, DDR2-800 TBD
Symbol
V
IH
(DC)
V
IH
(DC)
V
IL
(DC)
V
IL
(DC)
Min
V
REF
+ 0.250
V
REF
+ 0.200
-
-
Max
-
-
V
REF
- 0.250
V
REF
- 0.200
Units
V
V
V
V
October 2006
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
