X2804C
4K
X2804C
5 Volt, Byte Alterable E
2
PROM
DESCRIPTION
512 x 8 Bit
FEATURES
•
•
•
•
•
•
•
90ns Access Time
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or V
PP
Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
High Performance Advanced NMOS Technology
Fast Write Cycle Times
—16 Byte Page Write Operation
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 640ms Typical
—Effective Byte Write Cycle Time: 300
µ
s
Typical
DATA
Polling
—Allows User to Minimize Write Cycle Time
JEDEC Approved Byte-Wide Pinout
High Reliability
—Endurance: 10,000 Cycles
—Data Retention: 100 Years
The Xicor X2804C is a 512 x 8 E
2
PROM, fabricated with
an advanced, high performance N-channel floating gate
MOS technology. Like all Xicor Programmable nonvola-
tile memories it is a 5V only device. The X2804C
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs,
ROMs and EPROMs.
The X2804C supports a 16-byte page write operation,
typically providing a 300µs/byte write cycle, enabling the
entire memory to be written in less than 640ms. The
X2804C also features
DATA
Polling, a system software
support scheme used to indicate the early completion of
a write cycle.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PIN CONFIGURATION
PLASTIC DIP
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
X2804C
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
NC
WE
OE
NC
CE
I/O7
I/O6
I/O5
I/04
I/O3
6612 FHD F02.1
©Xicor, Inc. 1993, 1995 Patents Pending
6612-1.3 3/27/96 T2/C1/D1 NS
1
Characteristics subject to change without notice
X2804C
PIN DESCRIPTIONS
Addresses (A
0
–A
8
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When
CE
is HIGH, power con-
sumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
PIN NAMES
Symbol
A
0
–A
8
I/O
0
–I/O
7
WE
CE
OE
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
6612 PGM T01
FUNCTIONAL DIAGRAM
X BUFFERS
LATCHES AND
DECODER
A0–A8
ADDRESS
INPUTS
Y BUFFERS
LATCHES AND
DECODER
4.096-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
WE
VCC
VSS
6612 FHD F01
CONTROL
LOGIC
2
X2804C
DEVICE OPERATION
Read
Read operations are initiated by both
OE
and
CE
LOW
and
WE
HIGH. The read operation is terminated by
either
CE
or
OE
returning HIGH. This two line control
architecture eliminates bus contention in a system envi-
ronment. The data bus will be in a high impedance state
when either
OE
or
CE
is HIGH.
Write
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The X2804C supports both a
CE
and
WE
controlled write cycle. That is, the address is
latched by the falling edge of either
CE
or
WE,
whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either
CE
or
WE,
whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X2804C allows the entire
memory to be typically written in 450ms. Page write
allows two to sixteen bytes of data to be consecutively
written to the X2804C prior to the commencement of the
internal programming cycle. Although the host system
may read data from any other device in the system to
transfer to the X2804C, the destination page address of
the X2804C should be the same on each subsequent
strobe of the
WE
and
CE
inputs. That is, A
4
through A
10
must be the same for each transfer of data to the
X2804C during a page write cycle.
The page write mode can be entered during any write
operation. Following the initial byte write cycle, the host
can write an additional one to fifteen bytes in the same
manner as the first byte was written. Each successive
byte load cycle, started by the
WE
HIGH to LOW
transition, must begin within 20µs of the falling edge of
the preceding
WE.
If a subsequent
WE
HIGH to LOW
transition is not detected within 20µs, the internal auto-
matic programming cycle will commence. There is no
page write window limitation. The page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 20µs.
DATA
Polling
The X2804C features
DATA
Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed.
DATA
Polling allows a simple
bit test operation to determine the status of the X2804C,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O
7
(i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O
7
will reflect true data.
WRITE PROTECTION
There are three features that protect the nonvolatile data
from inadvertent writes.
• Noise Protection—A
WE
pulse which is typically
less than 10ns will not initiate a write cycle.
• V
CC
Sense—All functions are inhibited when V
CC
is
≤3V,
typically.
• Write Inhibit—Holding either
OE
LOW,
WE
HIGH,
or
CE
HIGH during power-up and power-down, will
inhibit inadvertent writes. Write cycle timing specifi-
cations must be observed concurrently.
ENDURANCE
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance.
3
X2804C
SYSTEM CONSIDERATIONS
Because the X2804C is frequently used in large memory
arrays, it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and elimi-
nate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit, it is recommended that
CE
be
decoded from the address bus and be used as the
primary device selection input. Both
OE
and
WE
would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X2804C has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling
CE
will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the l/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
quency ceramic capacitor be used between V
CC
and
V
SS
at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V
CC
and V
SS
for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
4
X2804C
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X2804C ....................................... –10°C to +85°C
X2804CI ..................................... –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS
.................................. –1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature (Soldering, 10 seconds)...... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
–40°C
Max.
+70°C
+85°C
6612 PGM T02.2
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Supply Voltage
X2804C
Limits
5V
±10%
6612 PGM T03
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
I
CC
Parameter
V
CC
Current (Active)
Min.
Typ.
(1)
70
Max.
110
Units
mA
Test Conditions
CE
=
OE
= V
IL
All I/O’s = Open
Other Inputs = V
CC
CE
= V
IH
,
OE
= V
IL
All I/O’s = Open
Other Inputs = V
CC
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
,
CE
= V
IH
I
SB
V
CC
Current (Standby)
35
50
mA
I
LI
I
LO
V
lL(2)
V
IH(2)
V
OL
V
OH
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
–1
2
2.4
10
10
0.8
V
CC
+1
0.4
µA
µA
V
V
V
V
I
OL
= 2.1mA
I
OH
= –400µA
6612 PGM T02.1
Notes:
(1) Typical values are for T
A
= 25°C and nominal supply voltage and are not tested.
(2) V
IL
min. and V
IH
max. are for reference only and are not tested.
5
