X51638
CPU Supervisor with 16Kb SPI EEPROM
FEATURES
• Extended Power-On Reset (800ms Nominal)
• Selectable Watchdog Timer
• Low Vcc Detection and Reset Assertion
—Five Standard Reset Threshold Voltages
—Re-program Low Vcc Reset Threshold Voltage
using special programming sequence
—Reset Signal Valid to Vcc=1V
• Determine Watchdog or Low Voltage Reset with
a Volatile Flag bit
• Long Battery Life With Low Power Consumption
—<50
m
A Max Standby Current, Watchdog On
—<1
m
A Max Standby Current, Watchdog Off
—<400
m
A Max Active Current during Read
• 16Kbits of EEPROM
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM Array with
Block Lock
TM
Protection
—In Circuit Programmable ROM Mode
• 2MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• Available Packages
—14-Lead TSSOP, 8-Lead SOIC
BLOCK DIAGRAM
WATCHDOG TRANSITION
DETECTOR
WATCHDOG
TIMER RESET
DESCRIPTION
This device combines four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervi-
sion, and Block Lock™ Protect Serial EEPROM in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates a power on reset
circuit which holds RESET active for a period of time.
This allows the power supply and oscillator to stabilize
before the processor can execute code. This device
allows 800ms before releasing the controller.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontrol-
ler fails to restart a timer within a selectable time-out
interval, the device activates the RESET signal. The user
selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
The X51638 low Vcc detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when Vcc falls below the minimum Vcc trip point.
RESET is asserted until Vcc returns to proper operating
level and stabilizes. Five industry standard V
TRIP
thresh-
olds are available, however, Xicor’s unique circuits allow
the thresold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
WP
SI
SO
SCK
CS/WDI
DATA
REGISTER
COMMAND
CONTROL
LOGIC
VCC THRESHOLD
RESET LOGIC
PROTECT LOGIC
RESET
STATUS
REGISTER
RESET &
WATCHDOG
TIMEBASE
4K BITS
8K BITS
EEPROM ARRAY
DECODE &
4K BITS
V
CC
V
TRIP
+
-
POWER ON AND
LOW VOLTAGE
RESET
GENERATION
Ó
Xicor, Inc. 1999 Patents Pending
9900-3002.10 2/12/99 T0/C0/D0
1
Characteristics subject to change without notice
X51638
PIN DESCRIPTION
PIN
(SOIC/PDIP)
PIN
TSSOP
Name
Function
1
1
CS/WDI
Chip Select Input.
CS HIGH, deselects the device and the SO output pin
is at a high impedance state. Unless a nonvolatile write cycle is underway,
the device will be in the standby power mode. CS LOW enables the device,
placing it in the active power mode. Prior to the start of any operation after
power up, a HIGH to LOW transition on CS is required
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the
Watchdog timer. The absence of a HIGH to LOW transition within the
watchdog time-out period results in RESET going active.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses,
and memory data on this pin. The rising edge of the serial clock (SCK) latches
the input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN
bit to “lock” the setting of the Watchdog Timer control and the memory write
protect bits.
Ground
Supply Voltage
Reset Output
. RESET is an active LOW open drain output which goes
active whenever Vcc falls below the minimum Vcc sense level. It will
remain active until Vcc rises above the minimum Vcc sense level for
800ms. RESET goes active if the Watchdog Timer is enabled and CS
remains either HIGH or LOW longer than the selectable Watchdog time-out
period. A falling edge of CS will reset the Watchdog Timer. RESET goes
active on power up at 1V and remains active for 800ms after the power
supply stabilizes.
No internal connections
2
5
2
8
SO
SI
6
9
SCK
3
4
8
6
7
14
WP
V
SS
V
CC
7
13
RESET
3-5,10-12
NC
PIN CONFIGURATION
14-LEAD TSSOP
8-LEAD SOIC/PDIP
CS
SO
WP
VSS
1
2
3
4
X51638
8
7
6
5
V CC
RESET
SCK
SI
CS
SO
NC
NC
NC
WP
VSS
1
2
3
4
5
6
7
X51638
14
13
12
11
10
9
8
V CC
RESET
NC
NC
NC
SCK
SI
2
X51638
PRINCIPLES OF OPERATION
POWER ON RESET
Application of power to the X51638 activates a Power On
Reset Circuit. This circuit goes active at V
CC
sense level
(V
TRIP
) and pulls the RESET pin LOW. This signal pre-
vents the system microprocessor from starting to operate
with insufficient voltage or prior to stabilization of the oscil-
lator. When Vcc exceeds the device V
TRIP
value for
800ms (nominal) the circuit releases RESET, allowing the
processor to begin executing code.
LOW VOLTAGE MONITORING
During operation, the X51638 monitors the V
CC
level and
asserts RESET if supply voltage falls below a preset mini-
mum V
TRIP
. The RESET signal prevents the microproces-
sor from operating in a power fail or brownout condition.
The RESET signal remains active until the voltage drops
below 1V. It also remains active until Vcc returns and
exceeds V
TRIP
for 800ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time-
out period. The state of two nonvolatile control bits in the
Status Register determine the watchdog timer period. The
microprocessor can change these watchdog bits, or they
may be “locked” by tying the WP pin LOW and setting the
WPEN bit HIGH.
VCC THRESHOLD RESET PROCEDURE
The X51638 is offered with one of several standard Vcc
threshold (V
TRIP
) voltages. This value will not change
over normal operating and storage conditions. However,
in applications where the standard V
TRIP
is not exactly
right, or for higher precision in the V
TRIP
value, the
X51638 threshold may be adjusted.
Setting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a higher voltage value.
For example, if the current V
TRIP
is 4.4V and the new
V
TRIP
is 4.6V, this procedure directly makes the change. If
the new setting is lower than the current setting, then it is
necessary to reset the trip point before setting the new
value.
CS
SCK
Vcc
Vp
SI
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold to the Vcc pin and tie the CS/WDI pin and the
WP pin HIGH. RESET and SO pins are left unconnected.
Then apply the programming voltage Vp to both SCK and
SI and pulse CS/WDI LOW then HIGH. Remove Vp and
the sequence is complete.
Figure 1. Set V
TRIP
Voltage
CS
Vp
SCK
Vp
SI
Resetting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a “native” voltage level.
For example, if the current V
TRIP
is 4.4V and the V
TRIP
is
reset, the new V
TRIP
is something less than 1.7V. This
procedure must be used to set the voltage to a lower
value.
To reset the V
TRIP
voltage, apply a voltage between 2.7
and 5.5V to the Vcc pin. Tie the CS/WDI pin, the WP pin,
AND THE SCK pin HIGH. RESET and SO pins are left
unconnected. Then apply the programming voltage Vp to
the SI pin ONLY and pulse CS/WDI LOW then HIGH.
Remove Vp and the sequence is complete.
Figure 2. Reset V
TRIP
Voltage
3
X51638
Figure 3. V
TRIP
Programming Sequence Flow Chart
V
TRIP
Programming
Execute
Reset V
TRIP
Sequence
Set Vcc = Vcc applied =
Desired V
TRIP
New Vcc applied =
Old Vcc applied + Error
Execute
Set V
TRIP
Sequence
New Vcc applied =
Old Vcc applied - Error
Apply 5V to Vcc
Execute
Reset V
TRIP
Sequence
Decrement Vcc
(Vcc = Vcc - 50mV)
NO
RESET pin
goes active?
YES
Error < 0
Measured V
TRIP
-
Desired V
TRIP
Error = 0
DONE
Error > 0
Figure 4. Sample V
TRIP
Reset Circuit
V
P
4.7K
1
X51638
8
7
6
5
NC
NC
4.7K
RESET
NC
2
3
4
V
TRIP
Adj.
Program
+
10K
10K
Reset
V
TRIP
Test
V
TRIP
Set
V
TRIP
4
X51638
SPI SERIAL MEMORY
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock
TM
Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
TM
cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families. It contains an 8-bit instruction
register that is accessed via the SI input, with data being
clocked in on the rising edge of SCK. CS must be LOW
during the entire operation.
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on the
first rising edge of SCK after CS goes LOW. Data is out-
put on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI instruc-
tion will reset the latch (Figure 3). This latch is automati-
cally reset upon a power-up condition and after the
completion of a valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status Reg-
ister. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
7
6
5
4
3
BL1
2
BL0
1
WEL
0
WIP
WPEN FLB
WD1 WD0
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
Table 1. Instruction Set
Instruction Name
WREN
SFLB
WRDI/RFLB
RSDR
WRSR
READ
WRITE
Instruction Format*
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
WREN CMD
WEL
0
1
1
1
STATUS
REGISTER
WPEN
X
1
0
X
DEVICE
PIN
WP#
X
0
X
1
BLOCK
PROTECTED
BLOCK
Protected
Protected
Protected
Protected
BLOCK
UNPROTECTED
BLOCK
Protected
Writable
Writable
Writable
STATUS
REGISTER
WPEN, BL0, BL1
WD0, WD1
Protected
Protected
Writable
Writable
5
