X88257
8051 Microcontroller Family Compatible
256K
X88257
E
2
Micro-Peripheral
DESCRIPTION
32,768 x 8 Bit
FEATURES
• Multiplexed Address/Data Bus
—Direct Interface to Popular 8051 Family
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500
µ
A Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 128 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
• 28-Lead PDIP Package
• 28-Lead SOIC Package
• 32-Lead PLCC Package
The X88257 is an 32K x 8 E
2
PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X88257 features a multiplexed address and
data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
FUNCTIONAL DIAGRAM
CE, CE
WR
RD
PSEN
A8–A14
CONTROL
LOGIC
X
D
E
C
O
D
E
SOFTWARE
DATA
PROTECT
ALE
L
A
T
C
H
E
S
32K x 8
E2PROM
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
6509 ILL F02.1
© Xicor, Inc. 1994-1997 Patents Pending
6509-1.9 4/9/96 T2/C5/D8 NS
1
Characteristics subject to change without notice
X88257
PIN DESCRIPTIONS
Address/Data (A/D
0
–A/D
7
)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while ALE is HIGH. After
ALE transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on
RD, WR, PSEN,
and
CE.
Addresses (A
8
–A
14
)
High order addresses flow into the device when ALE =
V
IH
and are latched when ALE goes LOW.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, ALE is LOW, and
CE is LOW, the X88257 is placed in the low power
standby mode. If
CE
is used to select the device, the CE
must be tied LOW.
Chip Enable (CE)
Chip enable is active HIGH. When CE is used to select
the device, the
CE
must be tied HIGH.
Program Store Enable (PSEN)
When the X88257 is to be used in a 8051-based system,
PSEN
is tied directly to the microcontroller’s
PSEN
output.
Read (RD)
When the X88257 is to be used in a 8051-based system,
RD
is tied directly to the microcontroller’s
RD
output.
Write (WR)
When the X88257 is to be used in a 8051-based system,
WR
is tied directly to the microcontroller’s
WR
output.
Address Latch Enable (ALE)
Addresses flow through the latches to address decoders
when ALE is HIGH and are latched when ALE transitions
from a HIGH to LOW.
PIN NAMES
Symbol
ALE
A/D
0
–A/D
7
A
8
–A
14
RD
WR
PSEN
CE,
CE
V
SS
V
CC
NC
2
PSEN
CE
NC
NC
NC
NC
NC
NC
A/D0
5
6
7
8
9
10
11
12
X88257
A14
A12
ALE
PSEN
CE
NC
NC
NC
NC
NC
A/D0
A/D1
A/D2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN CONFIGURATION
PDIP
SOIC
28
27
26
25
24
23
X88257
22
21
20
19
18
17
16
15
VCC
WR
A13
A8
A9
A11
RD
A10
CE
A/D7
A/D6
A/D5
A/D4
A/D3
6509 FHD F01.3
PLCC
ALE
VCC
A12
A14
WR
A13
NC
4
3
2
1 32 31 30
29
28
27
26
25
24
23
22
A8
A9
A11
NC
RD
A10
CE
A/D7
A/D6
13
21
14 15 16 17 18 19 20
A/D1
A/D2
VSS
NC
A/D3
A/D4
A/D5
6509 FHD F01A.5
Description
Address Latch Enable
Address Inputs/Data I/O
Address Inputs
Read Input
Write Input
Program Store Enable Input
Chip Enable
Ground
Supply Voltage
No Connect
6509 PGM T01.1
X88257
TYPICAL APPLICATION
U?
31
19
EA/VP
X1
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE/P
TXD
RXD
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
11
12
12
15
16
17
18
19
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
18
9
X2
RESET
12
13
14
15
1
2
3
4
5
6
7
8
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
8051
25
A8
24
A9
21
A10
23
A11
2
A12
26
A13
1
A14
20
CE
CE
22
RD
27
WR
4
PSEN
3
ALE
X88257
6509 ILL F03.3
5
PRINCIPLES OF OPERATION
The X88257 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The X88257
provides 32K-bytes of 5V E
2
PROM which can be used
either for program storage, data storage or a combina-
tion of both, in systems based upon Harvard (80XX)
architectures. The X88257 incorporates the interface
circuitry normally needed to decode the control signals
and demultiplex the address/data bus to provide a
“seamless” interface.
The interface inputs on the X88257 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip micro-
controller. In the Harvard type system, the reading of
data from the chip is controlled either by the
PSEN
or the
RD
signal, which essentially maps the X88257 into both
the Program and the Data Memory address map.
The X88257 also features the industry standard 5V
E
2
PROM characteristics such as byte or page mode
write and Toggle Bit Polling.
3
DEVICE OPERATION
Modes—Mixed Program/Data Memory
By properly assigning the address spaces, a single
X88257 can be used as both the program and data
memory. This would be accomplished by connecting all
the 8051 control outputs to the corresponding inputs of
the X88257.
Program Memory Mode
This mode of operation is read-only. The
PSEN
and
ALE
inputs of the X88257 are tied directly to the
PSEN
and
ALE outputs of the microcontroller. The
RD
and
WR
inputs are tied HIGH.
When ALE is HIGH, the A/D
0
–A/D
7
and A
8
–A
14
ad-
dresses flow into the device. The addresses, both low-
and high-order, are latched when ALE transitions LOW
(V
IL
).
PSEN
will then go LOW and after t
PLDV
; Valid data
is presented on the A/D
0
–A/D
7
pins.
CE
must be LOW
during the entire operation.
X88257
DATA MEMORY MODE
This mode of operation allows both read and write
functions. The
PSEN
input is tied to V
IH
or to V
CC
through a pull-up resistor. The ALE,
RD,
and
WR
inputs
are tied directly to the microcontroller ALE,
RD,
and
WR
outputs.
Read
This operation is quite similar to the program memory
read. A HIGH to LOW transition on ALE latches the
addresses and the data will be output on the AD pins
after
RD
goes LOW (t
RLDV
).
Write
A write is performed by latching the addresses on the
falling edge of ALE. Then
WR
is strobed LOW followed
by valid data being presented at the A/D
0
–A/D
7
pins.
The data will be latched into the X88257 on the rising
edge of
WR.
To write to the X88257, a three-byte
command sequence must precede the byte(s) being
written. (See Software Data Protection.)
MODE SELECTION
CE
V
CC
HIGH
LOW
LOW
LOW
PSEN
X
X
LOW
HIGH
HIGH
RD
X
X
HIGH
LOW
HIGH
WR
X
X
HIGH
HIGH
Mode
Standby
Standby
Read
Read
Write
I/O
High Z
High Z
D
OUT
D
OUT
D
IN
Power
Standby (CMOS)
Standby (TTL)
Active
Active
Active
6509 PGM T02
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X88257
supports page mode write operations. This allows the
microcontroller to write from 1 to 128 bytes of data to the
X88257. Each individual write within a page write opera-
tion must conform to the byte write timing requirements.
The falling edge of
WR
starts a timer delaying the
internal programming cycle 100µs. Therefore, each
successive write operation must begin within 100µs of
the last byte written. The following waveforms illustrate
the sequence and timing requirements.
Page Write Timing Sequence for
WR
Controlled Operation
OPERATION
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
CE
ALE
A/D0–A/D7
AIN
DIN
AIN
DIN
AIN
DIN
AIN
DIN
AIN
DOUT
AIN
AIN
A8–A14
An
An
An
An
An
ADDR
Next Address
WR
PSEN(RD)
tBLC
tWC
6509 ILL F08.1
Notes:
(1) For each successive write within a page write cycle A
7
–A
14
must be the same.
4
X88257
TOGGLE BIT POLLING
Because the typical write timing is less than the specified
5ms, Toggle Bit Polling has been provided to determine
the early end of write. During the internal programming
cycle I/O
6
will toggle from “1” to “0” and “0” to “1” on
Toggle Bit Polling
RD/WR
Control
OPERATION
LAST BYTE
WRITTEN
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X88C64 READY FOR
NEXT OPERATION
subsequent attempts to read the device. When the
internal cycle is complete the toggling will cease and the
device will be accessible for additional read or write
operations.
CE
ALE
A/D0–A/D7
AIN
DIN
AIN
DOUT
AIN DOUT
AIN DOUT
AIN
DOUT
AIN
A8–A14
An
An
An
An
An
ADDR
WR
RD
6509 ILL F09.1
SOFTWARE DATA PROTECTION
Software Data Protection (SDP) is employed to protect
the entire array against inadvertent writes. To write to the
X88257, a three-byte command sequence must precede
the byte(s) being written. All write operations, both the
command sequence and any data write operations must
conform to the page write timing requirements.
Writing with SDP
WRITE AA
TO 5555
WRITE 55
TO 2AAA
WRITE A0
TO 5555
PERFORM BYTE
OR PAGE WRITE
OPERATIONS
WAIT tWC
EXIT ROUTINE
6509 ILL F10.1
5
