DATASHEET
X9318
Digitally Controlled Potentiometer (XDCP™)
FEATURES
•
•
•
•
•
•
Solid-state potentiometer
3-wire serial interface
Terminal voltage, 0 to +8V
100 wiper tap points
—Wiper position stored in nonvolatile memory
and recalled on power-up
99 resistive elements
—Temperature compensated
—End to end resistance range ± 20%
Low power CMOS
—V
CC
= 5V
—Active current, 3mA max.
—Standby current, 1mA max.
High reliability
—Endurance, 100,000 data changes per bit
—Register data retention, 100 years
R
TOTAL
value = 10k
Packages
—8 Ld SOIC and DIP
Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The Intersil X9318 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory.
The wiper position is controlled by a 3-wire interface.
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switch-
ing network. Between each element and at either end
are tap points accessible to the wiper terminal. The
position of the wiper element is controlled by the CS,
U/D, and INC inputs. The position of the wiper can be
stored in nonvolatile memory and then be recalled
upon a subsequent power-up operation.
The device can be used as a three-terminal potentiome-
ter for voltage control or as a two-terminal variable resis-
tor for current control in a wide variety of applications.
PIN CONFIGURATION
DIP/SOIC
INC
U/D
R
H
V
SS
1
2
3
4
X9318
8
7
6
5
V
CC
CS
R
L
R
W
FN8184
Rev 1.00
September 14, 2005
•
•
•
•
APPLICATIONS
•
•
•
•
•
LCD bias control
DC bias adjustment
Gain and offset trim
Laser diode bias control
Voltage regulator output control
BLOCK DIAGRAM
V
CC
(Supply Voltage)
U/D
INC
CS
R
H
Control
and
Memory
R
W
R
L
V
SS
(Ground)
General
Store and
Recall
Control
Circuitry
7-Bit
Nonvolatile
Memory
Up/Down
Counter
99
98
97
96
One
of
One
Hundred
Decoder
2
V
CC
V
SS
1
0
R
L
R
W
Detailed
R
H
Up/Down
(U/D)
Increment
(INC)
Device Select
(CS)
Wiper
Switches
Resistor
Array
FN8184 Rev 1.00
September 14, 2005
Page 1 of 10
X9318
Ordering Information
PART NUMBER
X9318WP8
X9318WP8I
X9318WS8*
X9318WS8Z* (Note)
X9318WS8I*
X9318WS8IZ* (Note)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART MARKING
X9318WP
X9318WP I
X9318W
X9318W Z
X9318W I
X9318W Z I
R
TOTAL
(k)
10
TEMP RANGE (°C)
0 to 70
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
8 Ld PDIP
8 Ld PDIP
8 Ld SOIC (150 mil)
8 Ld SOIC (150 mil) (Pb-free)
8 Ld SOIC (150 mil)
8 Ld SOIC (150 mil) (Pb-free)
PACKAGE
PIN DESCRIPTIONS
DIP/SOIC
1
2
3
4
5
6
7
8
Symbol
INC
U/D
R
H
V
SS
R
W
R
L
CS
V
CC
Brief Description
Increment.
Toggling INC while CS is low moves the wiper either up or down.
Up/Down.
The U/D input controls the direction of the wiper movement.
The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
Ground.
The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.
The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
Chip Select.
The device is selected when the CS input is LOW, and de-selected when CS is high.
Supply Voltage.
FN8184 Rev 1.00
September 14, 2005
Page 2 of 10
X9318
ABSOLUTE MAXIMUM RATINGS
Junction Temperature under bias...... -65C to +135C
Storage temperature ......................... -65°C to +150°C
Voltage on CS, INC, U/D and V
CC
with respect to V
SS
................................. -1V to +7V
R
H
, R
W
, R
L
to ground..........................................+10V
Lead temperature (soldering 10s) ..................... 300°C
I
W
(10s) ..............................................................±6mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
POTENTIOMETER CHARACTERISTICS
(V
CC
= 5V ± 10%, T
A
= Full Operating Temperature Range unless otherwise stated)
Limits
Symbol
Parameter
End to end resistance tolerance
V
RH
/
RL
R
W
I
W
R
H
/R
L
terminal voltage
Power rating
Wiper resistance
Wiper current
(5)
Noise
(7)
Resolution
Absolute linearity
(1)
Relative linearity
(2)
R
TOTAL
temperature coefficient
(5)
Ratiometric temperature coeffi-
cient
(5),(6)
C
H
/C
L
/C
W(5
Potentiometer capacitances
)
Min.
-20
V
SS
Typ.
(4)
Max.
+20
8
25
Unit
%
V
mW
mA
dBV
%
Test Conditions/Notes
See ordering information
for values
V
SS
= 0V
I
W
= 1mA
See test circuit
Ref: 1kHz
V(RH) = 8V,
V(RL) = 0V
40
-3.0
-120
1
-1
-0.2
±300
-20
10/10/25
4.5
200
+3.0
+1
+0.2
+20
MI
(3)
MI
(3)
ppm/°C
ppm/°C
pF
See equivalent circuit
V
CC
Supply Voltage
5.5
V
FN8184 Rev 1.00
September 14, 2005
Page 3 of 10
X9318
D.C. OPERATING CHARACTERISTICS
(V
CC
= 5V ± 10%, T
A
= Full Operating Temperature Range unless otherwise stated)
Limits
Symbol
I
CC
I
SB
I
LI
V
IH
V
IL
C
IN
(5)
Parameter
V
CC
active current (Increment)
Standby supply current
CS, INC, U/D input leakage current
CS, INC, U/D input HIGH voltage
CS, INC, U/D input LOW voltage
CS, INC, U/D input capacitance
Min.
Typ.
(4)
1
Max.
3
Unit
mA
Test Conditions
CS = V
IL
, U/D = V
IL
or V
IH
and
INC = 0.4V/2.4V @ min. t
CYC
R
L
, R
H
, R
W
not connected
CS
2.4V, U/D and INC = 0.4V
R
L
, R
H
, R
W
not connected
V
IN
= V
SS
to V
CC
300
-10
2
-1
1000
+10
V
CC
+ 1
0.8
10
µA
µA
V
V
pF
V
CC
= 5V, V
IN
= V
SS
, T
A
= 25°C,
f = 1MHz
ENDURANCE AND DATA RETENTION
(V
CC
= 5V ± 10%, T
A
= Full Operating Temperature Range)
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit
Years
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R
W(n)(actual)
) - V(R
W(n)(expected)
)]/MI
V(R
W(n)(expected)
) = n(V(R
H
) - V(R
L
))/99 + V(R
L
), with n from 0 to 99.
(2) Relative linearity is a measure of the error in step size between taps = [V(R
W(n+1)
) - (V(R
W(n)
) - MI)]/MI
(3) 1 Ml = Minimum Increment = [V(R
H
) - V(R
L
)]/99.
(4) Typical values are for T
A
= 25°C and nominal supply voltage.
(5) This parameter is not 100% tested.
(6) Ratiometric temperature coefficient = (V(R
W
)
T1(n)
- V(R
W
)
T2(n)
)/[V(R
W
)
T1(n)
(T1 - T2) x 10
6
], with T1 & T2 being 2 temperatures, and n
from 0 to 99.
(7) Measured with wiper at tap position 31, R
L
grounded, using test circuit.
Test Circuit
Equivalent Circuit
R
TOTAL
R
H
C
H
Force
Current
10pF
R
W
C
W
25pF
C
L
10pF
R
L
Test Point
R
W
A.C. CONDITIONS OF TEST
Input pulse levels
Input rise and fall times
Input reference levels
0.8V to 2.0V
10ns
1.4V
FN8184 Rev 1.00
September 14, 2005
Page 4 of 10
X9318
A.C. OPERATING CHARACTERISTICS
(V
CC
= 5V ± 10%, T
A
= Full Operating Temperature Range unless otherwise stated)
Limits
Symbol
t
Cl
t
lD
(5)
t
DI
(5)
t
lL
t
lH
t
lC
t
CPHS
t
CPHNS
(5
)
Parameter
CS to INC setup
INC HIGH to U/D change
U/D to INC setup
INC LOW period
INC HIGH period
INC inactive to CS inactive
CS deselect time (STORE)
CS deselect time (NO STORE)
INC to R
W
change
INC cycle time
INC input rise and fall time
Power-up to wiper stable
V
CC
power-up rate
Min.
100
100
1
1
1
1
20
1
Typ.
(4)
Max.
Unit
ns
ns
µs
µs
µs
µs
ms
µs
t
IW
t
CYC
t
R
,
t
F
(5)
t
PU
(5)
t
R
V
CC
(5)
100
4
500
500
500
µs
µs
µs
µs
V/ms
0.2
50
POWER-UP AND DOWN REQUIREMENTS
The recommended power-up sequence is to apply V
CC
/V
SS
first, then the potentiometer voltages. During power-up,
the data sheet parameters for the DCP do not fully apply until 1 millisecond after V
CC
reaches its final value. The V
CC
ramp spec is always in effect. In order to prevent unwanted tap position changes, or an inadvertant store, bring the
CS and INC high before or concurrently with the V
CC
pin on powerup.
A.C. TIMING
CS
t
CYC
t
CI
INC
t
ID
U/D
t
IW
R
W
MI
(3)
t
DI
t
F
t
IL
t
IH
t
IC
t
CPHS
90%
90%
10%
t
R
t
CPHNS
FN8184 Rev 1.00
September 14, 2005
Page 5 of 10
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