X9420
NOT RECOMMENDED FOR NEW DESIGNS
POSSIBLE SUBSTITUTE PRODUCT
ISL22416, ISL22419, ISL95311, ISL95711
DATASHEET
FN8195
Rev.1.00
April 26, 2006
Low Noise/Low Power/SPI Bus Single Digitally Controlled (XDCP™)
Potentiometer
FEATURES
• Solid-State Potentiometer
• SPI Serial Interface
• Register Oriented Format
—Direct read/write/transfer wiper positions
—Store as many as four positions per
potentiometer
• Power Supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low Power CMOS
—Standby current < 1µA
• High Reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 8-bytes of Nonvolatile EEPROM Memory
• 10k or 2.5k Resistor Arrays
• Resolution: 64 Taps Each Pot
• 14 Ld TSSOP and 16 Ld SOIC Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9420 integrates a single digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
HOLD
CS
SCK
S0
SI
A0
Interface
and
Control
Circuitry
R0 R1
8
Data
R2 R3
Wiper
Counter
Register
(WCR)
V
H
/R
H
V
L
/R
L
V
W
/R
W
FN8195 Rev.1.00
April 26, 2006
Page 1 of 19
X9420
Ordering Information
PART NUMBER
X9420WS16*
X9420WS16Z* (Note)
X9420WS16I*
X9420WS16IZ* (Note)
X9420WV14*
X9420WV14Z* (Note)
X9420WV14I*
X9420WV14IZ* (Note)
X9420YS16*
X9420YS16Z* (Note)
X9420YS16I*
X9420YS16IZ* (Note)
X9420YV14*
X9420YV14Z* (Note)
X9420YV14I*
X9420YV14IZ* (Note)
X9420WS16-2.7*
PART
MARKING
X9420WS
X9420WS Z
X9420WS I
X9420WS ZI
X9420 W
X9420 WZ
X9420 WI
X9420 WZI
X9420YS
X9420YS Z
X9420YS I
X9420YS ZI
X9420 Y
X9420 YZ
X9420 YI
X9420 YZI
X9420WS F
2.7 to 5.5
10
2.5
POTENTIOMETER
ORGANIZATION TEMP. RANGE
(k)
(°C)
V
CC
LIMITS (V)
5 ±10%
10
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
2.7 to 5.5
2.5
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
PACKAGE
16 Ld SOIC (300 mil)
16 Ld SOIC (300 mil) (Pb-free)
16 Ld SOIC (300 mil)
16 Ld SOIC (300 mil) (Pb-free)
14 Ld TSSOP (4.4mm)
PKG.
DWG. #
M16.3
M16.3
M16.3
M16.3
M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
16 Ld SOIC (300 mil)
16 Ld SOIC (300 mil) (Pb-free)
16 Ld SOIC (300 mil)
16 Ld SOIC (300 mil) (Pb-free)
14 Ld TSSOP (4.4mm)
M16.3
M16.3
M16.3
M16.3
M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
16 Ld SOIC (300 mil)
16 Ld SOIC (300 mil) (Pb-free)
16 Ld SOIC (300 mil)
16 Ld SOIC (300 mil) (Pb-free)
14 Ld TSSOP (4.4mm)
M16.3
M16.3
M16.3
M16.3
M14.173
X9420WS16Z-2.7* (Note) X9420WS ZF
X9420WS16I-2.7*
X9420WS16IZ-2.7*
(Note)
X9420WV14-2.7*
X9420WS G
X9420WS ZG
X9420 WF
X9420WV14Z-2.7* (Note) X9420 WZF
X9420WV14I-2.7*
X9420WV14IZ-2.7*
(Note)
X9420YS16-2.7*
X9420 WG
X9420 WZG
X9420YS F
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
16 Ld SOIC (300 mil)
16 Ld SOIC (300 mil) (Pb-free)
16 Ld SOIC (300 mil)
16 Ld SOIC (300 mil) (Pb-free)
14 Ld TSSOP (4.4mm)
M16.3
M16.3
M16.3
M16.3
M14.173
X9420YS16Z-2.7* (Note) X9420YS ZF
X9420YS16I-2.7*
X9420YS G
X9420YS16IZ-2.7* (Note) X9420YS ZG
X9420YV14-2.7*
X9420 YF
X9420YV14Z-2.7* (Note) X9420 YZF
X9420YV14I-2.7*
X9420 YG
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm)
M14.173
X9420YV14IZ-2.7* (Note) X9420 YZG
*Add "T1" suffix for tape and reel.
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8195 Rev.1.00
April 26, 2006
Page 2 of 19
X9420
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched by
the rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9420.
Chip Select (CS)
When CS is HIGH, the X9420 is deselected and the SO
pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby
state. CS LOW enables the X9420, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
Device Address (A
0
)
The address inputs is used to set the least significant bit
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address input
in order to initiate communication with the X9420. A
maximum of 2 devices may occupy the SPI serial bus.
Potentiometer Pins
V
H
/R
H
, V
L
/R
L
The V
H
/R
H
and V
L
/R
L
input are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
/R
W
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
System/Digital Supply (V
CC
)
V
CC
is the supply voltage for the system/digital section.
V
SS
is the system ground.
PIN CONFIGURATION
DIP/SOIC
V
CC
CS
R
L
/V
L
R
H
/V
H
R
W
/V
W
SI
WP
V
SS
1
2
3
4
5
6
7
8
X9420
16
15
14
13
12
11
10
9
V+
NC
A0
SO
HOLD
SCK
NC
V-
TSSOP
CS
R
L
/V
L
R
H
/V
H
R
W
/V
W
SI
WP
V
SS
1
2
3
4
5
6
7
14
13
12
X9420
11
10
9
8
V
CC
V+
A0
SO
HOLD
SCK
V-
FN8195 Rev.1.00
April 26, 2006
Page 3 of 19
X9420
PIN NAMES
Symbol
SCK
SI, SO
A0
V
H
/R
H
,
V
L
/R
L
V
W
/R
W
WP
HOLD
V+,V-
V
CC
V
SS
NC
Serial Clock
Serial Data
Device Address
Potentiometer Pins (terminal equivalent)
Potentiometer Pins (wiper equivalent)
Hardware Write Protection
Serial Communication Pause
Analog Supplies
System Supply Voltage
System Ground
No Connection
Wiper Counter Register (WCR)
Description
The X9420 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The contents
of the WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data
registers via the XFR Data Register instruction (parallel
load); it can be modified one step at a time by the
Increment/ Decrement instruction. Finally, it is loaded
with the contents of its data register zero (DR0) upon
power-up.
The Wiper Counter Register is a volatile register; that is,
its contents are lost when the X9420 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
Data Registers
The potentiometer has four 6-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can
also be transferred between any of the four Data Registers
and the WCR. It should be noted all operations changing
data in one of the Data Registers is a nonvolatile operation
and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system
parameters or user preference data.
Register Descriptions
Table 1. Data Registers, (6-bit), Nonvolatile
0
(MSB)
PRINCIPLES OF OPERATION
The X9420 is a highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing direct
communication between the host and the XDCP
potentiometer.
Serial Interface
The X9420 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9420 is comprised of one resistor array containing
63 discrete resistive segments that are connected in
series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer
(V
H
/R
H
and V
L
/R
L
inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within the individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches. The block diagram of the
potentiometer is shown in Figure 1.
0
D5
D4
D3
D2
D1
D0
(LSB)
There are four 6-bit Data Registers associated with the
potentiometer.
– {D5~D0}: These bits are for general purpose Nonvola-
tile data storage or for storage of up to four different
wiper values.
Table 2. Wiper Counter Register, (6-bit), Volatile
0
(MSB)
0
WP5 WP4 WP3 WP2 WP1 WP0
(LSB)
– {WP5~WP0}: These bits specify the wiper position of
the potentiometer.
FN8195 Rev.1.00
April 26, 2006
Page 4 of 19
X9420
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 1
6
Serial
Bus
Input
C
O
U
N
T
E
R
D
E
C
O
D
E
V
H
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
REGISTER 2
REGISTER 3
IF WCR = 00[H] THEN V
W
= V
L
IF WCR = 3F[H] THEN V
W
= V
H
UP/DN
Modified SCK
INC/DEC
Logic
UP/DN
CLK
V
L
V
W
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by the
device. The progress of this internal write operation can
be monitored by a Write In Process bit (WIP). The WIP bit
is read with a Read Status command.
INSTRUCTIONS
Address/Identification (ID) Byte
The first byte sent to the X9420 from the host, following
a CS going HIGH to LOW, is called the Address or
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the X9420
this is fixed as 0101[B] (refer to Figure 2).
The least significant bit in the ID byte selects one of two
devices on the bus. The physical device address is
defined by the state of the A
0
input pin. The X9420
compares the serial data stream with the address input
state; a successful compare of the address bit is
required for the X9420 to successfully continue the
command sequence. The A
0
input can be actively driven
by a CMOS input signal or tied to V
CC
or V
SS
.
The remaining three bits in the ID byte must be set to 110.
The four high order bits of the instruction byte specify the
operation. The next two bits (R
1
and R
0
) select one of
the four registers that is to be acted upon when a
FN8195 Rev.1.00
April 26, 2006
Figure 2. Address/Identification Byte Format
Device Type
Identifier
0
1
0
1
1
1
0
A0
Device Address
Instruction Byte
The next byte sent to the X9420 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next two bits point
to one of four data registers. The format is shown below
in Figure 3.
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
0
0
Instructions
register oriented instruction is issued. The last two bits
are defined as 0.
Page 5 of 19
