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X9428
XDCP
™
Digitally Controlled Potentiometer
FEATURES
• Two-Wire Serial Interface
• Hardware Write Protection, WP
• Register Oriented Format
—Directly Read/Write Wiper Position
—Store as Many as Four Positions
• Power Supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = –2.7V to –5.5V
• Direct Write Cell
—Endurance - 100,000 Data Changes per
Register
—Register Data Retention - 100 years
• 16 Bytes of E
2
PROM memory
• 3 Resistor Array Values
—2K Ohms to 50K Ohms Mask Programmable
• Resolution: 64 Taps each Pot
• 24-Pin Plastic DIP, 24-Lead TSSOP and
24-Lead SOIC Packages
• Low Power CMOS
—Standby Current < 1µA
DESCRIPTION
The X9428 nonvolatile XDCP, digitally controlled
potentiometer contains a resistor array, composed of
63 resistive elements. Between each element and at
either end are tap points accessible to the wiper ele-
ments. The position of the wiper element on the array
is controlled by the user through the two wire serial
bus interface.
The resistor array has associated with it a nonvolatile
control latch and four 6 bit data registers that can be
directly written and read by the user. The contents of
the control latch controls the position of the resistor
array/wiper.
FUNCTIONAL DIAGRAM
R0
R1
R2
SCL
SDA
WIPER
COUNTER
REGISTER
(WCR)
R3
VH
VL
VW
A0
A1
A2
A3
INTERF
ACE
AND
CONTROL
CIRCUITR
Y
8
DATA
©
Xicor, Inc. 1994, 1995, 1996 Patents Pending
70290-1.1 9/23/99 EP
1
Characteristics subject to change without notice
X9428
PIN DESCRIPTIONS
Analog Supply V+, V-
The Analog Supply V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
DIP/SOIC
VCC
A2
V
L
V
H
V
W
SDA
WP
V SS
1
2
3
4
5
6
7
8
X9428
16
15
14
13
12
11
10
9
V+
NC
A0
NC
A1
SCL
NC
V–
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9428.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val-
ues, refer to the guidelines for calculating typical val-
ues on the bus pull-up resistors graph.
Device Address (A
0
–A
3
)
The Address inputs are used to set the least signifi-
cant 4 bits of the 8-bit slave address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9428. A maximum of 16 devices may occupy
the 2-wire serial bus.
PIN NAMES
Symbol
SCL
SDA
A0-A2
V
H
, V
L
V
W
WP
V+,V-
VCC
Vss
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometers
(terminal equivalent)
Potentiometers
(Wiper equivalent)
Hardware Write Protection
Analog and Voltage Follower
Supplys
System Supply Voltage
System Ground
No Connection
Potentiometer Pins
V
H
(V
H0
– V
H1
), V
L
(V
L0
– V
L1
)
The VH and VL inputs are equivalent to the terminal
connections on either end of a mechanical potentiom-
eter.
V
W
(V
W0
– V
W1
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer and the non-inverting
input of the voltage follower.
Hardware Write Protect Input WP
The
WP
pin when low prevents nonvolatile writes to
the wiper and voltage follower control latchs.
2
X9428
PRINCIPLES OF OPERATION
The X9428 is a highly integrated microcircuit incorpo-
rating a resistor array and associated registers and
counters and the serial interface logic providing direct
communication between the host and XDCP.
Serial Interface
The X9428 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive opera-
tions. Therefore, the X9428 will be considered a slave
device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
LOW
). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
HIGH
). The X9428 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condi-
tion is met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com-
mand byte. If the command is followed by a data byte
the X9428 will respond with a final acknowledge.
Array Description
The X9428 is comprised a resistor array containing 63
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(V
H
and V
L
inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
) output. Within the array only one switch may be
turned on at a time. These switches are controlled by
a nonvolatile control latch (NCL). The six bits of the
NCL are decoded to select, and enable, one of sixty-
four switches.
The NCL may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the NCL. These data registers and
the NCL can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9428 this
is fixed as 0101[B].
Figure 1. Slave Address
DEVICE TYPE
IDENTIFIER
0
1
0
1
A3
A2
A1
A0
DEVICE ADDRESS
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0-A2 inputs. The X9428 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9428 to respond with an acknowledge. The
A
0
–A
2
inputs can be actively driven by CMOS input
signals or tied to V
CC
or V
SS
.
3
X9428
Acknowledge Polling
The disabling of the inputs, during the internal non-vol-
atile write operation, can be used to take advantage of
the typical 5ms E
2
PROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9428 initiates the internal
write cycle. ACK polling can be initiated immediately.
This involves issuing the start condition followed by
the device slave address. If the X9428 is still busy with
the write operation no ACK will be returned. If the
X9428 has completed the write operation an ACK will
be returned and the master can then proceed with the
next operation.
Flow 1. ACK Polling Sequence
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four regis-
ters that is to be acted upon when a register oriented
instruction is issued. The last two bits are reserved
and not used.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the Control Latch and one of
the data registers. A transfer from a data register to a
Control Latch is essentially a write to a static RAM.
The response of the wiper to this action will be
delayed t
STPWV
. A transfer from Control Latch current
wiper position, to a data register is a write to nonvola-
tile memory and takes a minimum of t
WR
to complete.
The transfer can occur between the potentiometer and
its associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9428; either between the host and
one of the data registers or directly between the host
and the Control Latch. These instructions are: Read
Control Latch, read the current wiper position of the
pot Write Control Latch, change current wiper position
of the pot Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,
write a new value to the selected data register. The
sequence of operations is shown in Figure 4.
Instruction Structure
The next byte sent to the X9428 contains the instruc-
tion and register pointer information as shown in Fig-
ure 2.
Figure 2. Instruction Byte Format
REGISTER
SELECT
I3
I2
I1
I0
R1
R0
X
X
INSTR UCTIONS
RESERVED
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLA VE
ADDRESS
ISSUE ST OP
ACK
RETURNED?
YES
NO
FURTHER
OPERA TION?
YES
ISSUE
INSTR UCTION
NO
ISSUE ST OP
PROCEED
PROCEED
4
X9428
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
X
X
A
C
K
S
T
O
P
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the wiper up and/or down in one
segment steps; thereby, providing a fine tuning capa-
bility to the host. For each SCL clock pulse (t
HIGH
)
Table 1. Instruction Set
I
3
1
1
1
1
1
while SDA is HIGH, the wiper will move one resistor
segment towards the V
H
terminal. Similarly, for each
SCL clock pulse while SDA is LOW, the wiper will
move one resistor segment towards the V
L
terminal. A
detailed illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
Instruction
Read Control Latch
Write Control Latch
Read Data Register
Write Data Register
XFR Data Register to
Control Latch
XFR Control Latch to
Data Register
Global XFR Data Reg-
ister to Control Latch
Global XFR Control
Latch to Data Register
Increment/Decrement
Wiper
Notes:
(7)
(8)
I
2
0
0
0
1
1
Instruction Set
I
1
I
0
R
1
R
0
0
1
1
0
0
1
0
1
0
1
N/A
N/A
1/0
1/0
1/0
N/A
N/A
1/0
1/0
1/0
X
N/A
N/A
N/A
N/A
N/A
X
N/A
N/A
N/A
N/A
N/A
Operation
Read the contents of the Control Latch pointed to
by P
1
–P
0
Write new value to the Control Latch pointed to
by P
1
–P
0
Read the contents of the Register pointed to by
P
1
–P
0
and R
1
–R
0
Write new value to the Register pointed to by
P
1
–P
0
and R
1
–R
0
Transfer the contents of the Register pointed
to by P
1
–P
0
and R
1
–R
0
to its associated
Control Latch
Transfer the contents of the Control Latch
pointed to by P
1
–P
0
to the Register pointed
to by R
1
–R
0
Transfer the contents of all four Data Registers
pointed to by R
1
–R
0
to their respective Control
Latch
Transfer the contents of all Control Latchs to their
respective data Registers pointed to by R
1
–R
0
Enable Increment/decrement of the Control Latch
pointed to by P
1
–P
0
1
1
1
0
1/0
1/0
N/A
N/A
0
1
0
0
0
0
0
0
1
1
0
0
1/0
1/0
N/A
1/0
1/0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1/0 = data is one or zero
N/A = Not applicable or don't care; that is, a data register is not involved in the operation and need not be addressed (typical)
5
