®
XC7336
36-Macrocell CMOS EPLD
Product Specifications
Features
•
Ultra high-performance EPLD
– 5 ns pin-to-pin speed on all fast inputs
– 167 MHz maximum clock frequency
interconnected by the 100%-populated Universal Intercon-
nect Matrix (UIM
™
).
Each Fast Function Block has 24 inputs and contains nine
Macrocells configurable for registered or combinational
logic. The nine Macrocell outputs feed back to the UIM and
can simultaneously drive the output pads.
The UIM allows 100% connectivity between all function
blocks and input pins, providing the ability to utilize 100% of
the device while eliminating routing issues.
The XC7336 is designed in 0.8
µ
CMOS EPROM technol-
ogy, in speed grades ranging from 5 to15 ns. The XC7336Q
is also available now, providing lower power consumption in
-10, -12 and -15 ns speed grades.
Device logic is automatically configured to the user’s speci-
fications using the XEPLD software. The XEPLD software
is capable of optimizing and collapsing logic. The SMART-
switch software/hardware feature allows implementation of
buried combinatorial logic functions in the UIM, thus
increasing device utilization. The XEPLD software supports
third party schematic capture and HDL entry tools, as well
as direct equation-based text files. Using a workstation or
PC platform, designs are automatically mapped into the
XC7336 in a matter of minutes.
• New low power XC7336Q
• 100% routable with 100% utilization
• Incorporates four PAL-like 24V9 Fast Function Blocks
• 36 Output Macrocells
– Programmable I/O architecture
– 24 mA drive
• High-performance
µ
P compatible
• Peripheral Component Interface (PCI) compatible
• JEDEC standard 3.3 V or 5 V I/O operation
• Multiple security bits for design protection
• 44-pin leaded chip carrier and 44-pin quad flat pack
packages
General Description
The XC7336 is a member of the Xilinx XC7300 EPLD fam-
ily. It consists of four PAL-like 24V9 Fast Function Blocks
PQ44
PC44
PC44
PQ44
22
28
I/FI
19
12
FFB1
34
12
FFB2
15
I/FI
42
36
1
2
3
5
6
7
8
9
10
7
8
9
11
12
13
14
15
16
I/FO/FI
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
MC1-1
MC1-2
AND ARRAY
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
9
12
12
3
12
AND ARRAY
12
3
MC2-9
MC2-8
MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
9
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
FO/FOE1
9
9
29
30
33
34
35
36
37
38
39
23
24
27
28
29
30
31
32
33
12
FFB4
UIM
12
FFB3
MC3-9
FO/FOE0
I/FO/FI
I/FO/FI
I/FO/FI/MR
I/FO/FI
I/FO/FI
I/FO/FI
FO/FCLK0
FO/FCLK1
12
AND ARRAY
12
3
MC3-8
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-1
9
X5452
21
20
19
18
16
14
13
12
11
27
26
25
24
22
20
19
18
17
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO/FI
I/FO/FI
I/FO/FI
I/FO
MC4-1
MC4-2
MC4-4
MC4-5
MC4-6
MC4-7
MC4-8
MC4-9
9
AND ARRAY
MC4-3
12
12
3
9
9
40
43
44
1
2
3
4
5
6
34
37
38
39
40
41
42
43
44
Figure 1. XC7336 Functional Block Diagram
2-23
This document was created with FrameMaker 4 0 2
XC7336 CMOS EPLD
Fast Function Blocks (FFB)
The XC7336 provides four Fast Function Blocks which
have 24 inputs that can be individually selected from the
UIM, 12 fast input pins, or the 9 Macrocell feedbacks from
the Function Block. The programmable AND array in each
Fast Function Block generates 45 product terms to drive
nine Macrocells in each FFB. Each Macrocell (Figure 2),
can be configured for registered or combinatorial logic.
Five product terms from the programmable AND array are
allocated to each Macrocell. Four of these product terms
are ORed together and may be optionally inverted before
driving the input of a programmable D-type flip-flop. The
fifth product term drives the asynchronous active-High
programmable Reset or Set Input to the Macrocell flip-
flop. The flip-flop can be configured as a D-type or Toggle
flip-flop or transparent for combinatorial outputs.
The programmable clock source is one of two global Fast-
CLK signals (FCLK0 or FCLK1) that are distributed with
short delay and minimal skew over the entire chip.
I/O Block
The Fast Function Block Macrocells drive chip outputs
directly through 3-state output buffers. Each output buffer
can be individually controlled by one of two dedicated
active-High Fast Output Enable inputs or permanently
enabled or disabled. The Macrocell output can also be
routed back as an input to the Fast Function Block, and
the UIM.
Power-On Characteristics/Master Reset
The XC7336 device undergoes a short internal initializa-
tion sequence upon device powerup. During this time (t
RE-
SET
), the outputs remain 3-stated while the device is
configured from its internal EPROM array and all registers
are initialized. If the MR pin is tied to V
CCINT
, the initializa-
tion sequence is completely transparent to the user and is
completed in t
RESET
after V
CCINT
has reached 4.75 V. If
MR is held low while the device is powering up, the inter-
nal initialization sequence begins and outputs will remain
3-stated until the sequence is complete and MR is brought
High. V
CC
rise must be monotonic to insure the initializa-
tion sequence is performed correctly.
For additional flexibility, the MR pin is provided so the
EPLD can be reinitialized after power is applied. On the
falling edge of MR, all outputs become 3-stated and the
initialization sequence is started. The outputs will remain
3-stated until the internal initialization sequence is com-
plete and MR is brought High. The minimum MR pulse
width is t
WMR
. If MR is brought High after t
WMR
, but
before t
RESET
, the outputs will become active after t
RESET
.
2 Global
Fast OE
12 from Fast
Input Pins
2
AND Array
12
24
Inputs from
UIM
3
Sum-of-Products
from
Previous
Macrocell
9 from FFB
Macrocell
Feedback
5
9
5 Private
P-Terms per
Macrocell
Fast
Clocks
0 1
I/O Block
1 of 9 Macrocells
OE Control
0
1
D/T Q
Output
Polarity
S/R
I/O
Pin
P-Term
Assignment
Control
Feedback
to UIM
Sum-of-Products to
Succeeding Macrocell
Pin Feedback
to UIM
Register
Transparent
Control
X5218
Figure 2. Fast Function Block and Macrocell Schematic
2-24
From Previous
Macrocell
Single-Product Term Assignment
Fast Function Block. Each UIM input can be programmed
to connect to any UIM output. The delay through the inter-
connect matrix is constant.
When multiple inputs are programmed to be connected to
the same output, this output produces the logical AND of the
input signals. By choosing the appropriate signal polarities
at the input pins, Macrocell outputs and Fast Function Block
AND-array inputs, this AND logic can also be used to imple-
ment wide NAND, OR or NOR functions. This offers an addi-
tional level of logic without additional speed penalty.
D/T
4
Q
Output
Polarity
3.3 V or 5 V Interface Configuration
Eight-Product Term Assignment
S/R
D/T Q
4
The XC7336 can be used in systems with two different
supply voltages: 3.3 V and 5 V. Each XC7336 device has
separate V
CC
connections to the internal logic (V
CCINT
) and
to the I/O pads (V
CCIO
). V
CCINT
must always be con-
nected to a 5 V supply. V
CCIO
may be connected to either
3.3 V or 5 V, depending on the output interface require-
ment.
When V
CCIO
is connected to 5 V, the input thresholds are
TTL levels, and thus compatible with 3.3 V and 5 V logic.
The output High levels are also TTL compatible. When
V
CCIO
is connected to 3.3 V, the input thresholds are still
TTL levels, and the outputs pull up to the 3.3 V. This
makes the XC7336 ideal for interfacing directly to 3.3 V
components. In addition, the output structure is designed
so that the I/O can also safely interface to a mixed 3.3 V
and 5 V bus simultaneously.
Low Power (Q) Devices
The XC7336-10, -12 and -15 are available in a low power
variant, designated the XC7336Q.
Timing parameters for the XC7336 and the XC7336Q
devices are identical. However, the XC7336Q features
much lower power consumption. Using the XC7336Q will
prove advantageous to any system design where power
consumption and EM emissions are critical system
parameters.
Output
Polarity
X3374
Figure 3. Fast Function Block Product Term Assignment
Product Term Assignment
Each Macrocell sum-of-product OR gate can be ex-
panded using the Export product-term assignment fea-
ture. The Export function transfers product-terms in incre-
ments of four from one Macrocell to the neighboring
Macrocell (Figure 3). Complex logic functions requiring up
to 36 product-terms can be implemented using all nine
Macrocells within the Fast Function Block. When product-
terms are assigned to adjacent Macrocells, the product-
term normally dedicated to the Set or Reset function
becomes the input to the Macrocell register.
Universal Interconnect Matrix
The UIM receives input from Macrocell outputs, I/O pins,
and dedicated input pins. Acting as an unrestricted cross-
bar switch, the UIM generates 24 output signals to each
2-25
XC7336 CMOS EPLD
Power Management
The XC7336 features a power-management scheme
which permits non-speed-critical paths of a design to be
operated at reduced power. Overall power dissipation is
often reduced significantly, since, in most systems only a
few paths are speed critical.
Macrocells can individually be specified for high perfor-
mance or low power operation by adding attributes to the
logic schematic, or declaration statements to the behavioral
description. To minimize power dissipation, unused Func-
tion Blocks are turned off and unused Macrocells in used
Function Blocks are configured for low power operation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
For non-Q devices:
I
CC
(mA) = MC
HP
(4.3) + MC
LP
(3.5) +
MC (0.005 mA/MHz) f
For Q devices: (-10, -12, -15):
I
CC
(mA) = MC
HP
(2.0) + MC
LP
(1.6) +
MC (0.005 nA/MHz) f
Where:
MC
HP
MC
LP
MC
f
=
=
=
=
Macrocells in high-performance mode
Macrocells in low-power mode
Total number of Macrocells used
Clock frequency (MHz)
Design Security
The XC7336 has a multibit security system that controls
access to the configuration programmed into the device.
This security scheme uses multiple EPROM bits at vari-
ous locations within the EPROM array to offer a higher
degree of design security than other EPROM and fused-
based devices.
Prototyping and Programming
Xilinx offers the HW-120 programmer for use during
prototyping as well as support from major third party
programmer companies. For production volumes, Xilinx and
their licensed distributors offer factory programming of the
XC7336 devices.
For factory programming procedures, contact your local
Xilinx representative.
XEPLD Translator Software
The designer can create, implement, and verify digital logic
circuits for EPLD devices using the Xilinx XEPLD software.
Designs can be represented as schematics consisting of
XEPLD library components, as behavioral descriptions
(Boolean, HDL etc.), or as a combination of both tech-
niques. The XEPLD translator automatically optimizes, col-
lapses, and implements the design as well as writing a
programming file without user intervention. At the comple-
tion of the compilation process, the XEPLD translator
writes detailed report files for design analysis and docu-
mentation.
Figure 4 shows a typical power calculation for the XC7336
device, programmed as two 16-bit counters and operating
at the indicated clock frequency.
200
an
High Perform
ce
150
Typical I
CC
(mA)
Low Power
100
High Pe
rforman
ce
50
s
Q device
er
Low Pow
0
50
Clock Frequency (MHz)
100
X5767
Figure 4. Typical I
CC
vs Frequency for XC7336
2-26
Here are just a few of the XEPLD Development System
features:
•
Automatic Optimization and Mapping
Designs are automatically minimized and mapped into
the devices for optimal efficiency and high
performance. Critical logic functions are automatially
assigned to special resources such as high speed
clocks and global output enable signals. This allows
the user to concentrate on design functionality without
concern for physical implementation
•
N-to-1 PAL Conversion Utility
XEPLD automatically combines 20- and 24-pin
standard PAL files into one top-level design file,
checks for errors, and compiles the design into one or
more EPLDs. The N-to-1 PAL converter is ideal for
one step logic consolidation and board space
reduction.
•
Complete Design Control
Users have the option to override the automatic
features of XEPLD and selectively control any or all
device resources.
•
Multiple Platform Support
XEPLD runs on IBM Compatible PCs, Sun, HP700,
and IBM RS6000 platforms.
• Automatic use of UIM Resources – SMARTswitch
The Universal Interconnect Maticx (UIM) used in Xilinx
EPLDs provides an additional level of logic at no
additional delay. XEPLD automatically uses the
inherent logic capability of the UIM when possible to
reduce Macrocell requirements and increase speed.
Notice: The information contained in this data sheet pertains to products in the initial production phases of development.
These specifications are subject to change without notice. Verify with your local Xilinx sales office that you have the latest
data sheet before finalizing a design.
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
TS
T
STG
T
SOL
Parameter
Supply voltage with respect to GND
DC Input voltage with respect to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Value
-0.5 to 7.0
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
-65 to +150
+250
Units
V
V
V
°
C
°
C
Warning
:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed
under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
Recommended Operating Conditions
Symbol
V
CCINT
/
V
CCIO
V
CCIO
V
IL
V
IH
V
O
T
IN
Parameter
Supply voltage relative to GND
Supply voltage relative to GND
Supply voltage relative to GND
I/O supply voltage relative to GND
Low-level input voltage
High-level input voltage
Output voltage
Input signal transition time
Commercial
Industrial
Military
T
A
= 0
o
C to 70
o
C
T
A
= -40
o
C to 85
o
C
T
A
= -55
o
C to T
C
= +125
o
C
Min
4.75
4.50
4.50
3.0
0
2.00
0
Max
5.25
5.50
5.50
3.60
0.80
V
CC
+0.5
V
CCIO
50
Units
V
V
V
V
V
V
V
ns
2-27
