Artix-7 FPGAs Data Sheet:
DC and Switching Characteristics
DS181 (v1.5) February 1, 2013
Preliminary Product Specification
Introduction
Artix™-7 FPGAs are available in -3, -2, -1, and -2L speed
grades, with -3 having the highest performance. The -2L
devices can operate at either of two V
CCINT
voltages, 0.9V
and 1.0V and are screened for lower maximum static power.
When operated at V
CCINT
= 1.0V, the speed specification of
a -2L device is the same as the -2 speed grade. When
operated at V
CCINT
= 0.9V, the -2L static and dynamic
power is reduced.
Artix-7 FPGA DC and AC characteristics are specified in
commercial, extended, and industrial temperature ranges.
Except the operating temperature range or unless
otherwise noted, all the DC and AC electrical parameters
are the same for a particular speed grade (that is, the timing
characteristics of a -1 speed grade industrial device are the
same as for a -1 speed grade commercial device). However,
only selected speed grades and/or devices are available in
each temperature range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
This Artix-7 FPGA data sheet, part of an overall set of
documentation on the 7 series FPGAs, is available on the
Xilinx website at
www.xilinx.com/7.
All specifications are subject to change without notice.
DC Characteristics
Table 1:
Absolute Maximum Ratings
(1)
Symbol
FPGA Logic
V
CCINT
V
CCAUX
V
CCBRAM
V
CCO
V
REF
V
IN(2)(3)(4)(5)
V
CCBATT
Internal supply voltage
Auxiliary supply voltage
Supply voltage for the block RAM memories
Output drivers supply voltage for 3.3V HR I/O banks
Input reference voltage
I/O input voltage
I/O input voltage for V
REF
and differential I/O standards
Key memory battery backup supply
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
1.1
2.0
1.1
3.6
2.0
V
CCO
+ 0.5
2.625
2.0
V
V
V
V
V
V
V
V
Description
Min
Max
Units
GTP Transceiver
V
MGTAVCC
V
MGTAVTT
V
MGTREFCLK
V
IN
I
DCIN
I
DCOUT
Analog supply voltage for the GTP transmitter and receiver circuits
Analog supply voltage for the GTP transmitter and receiver termination circuits
Reference clock absolute input voltage
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
DC input current for receiver input pins DC coupled V
MGTAVTT
= 1.2V
DC output current for transmitter pins DC coupled V
MGTAVTT
= 1.2V
XADC supply relative to GNDADC
XADC reference input relative to GNDADC
–0.5
–0.5
–0.5
–0.5
–
–
1.1
1.32
1.32
1.26
10
10
V
V
V
V
mA
mA
XADC
V
CCADC
V
REFP
–0.5
–0.5
2.0
2.0
V
V
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DS181 (v1.5) February 1, 2013
Preliminary Product Specification
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 1:
Absolute Maximum Ratings
(1)
(Cont’d)
Symbol
Temperature
T
STG
T
SOL
T
j
Notes:
1.
2.
3.
4.
5.
6.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
The lower absolute voltage specification always applies.
For I/O operation, refer to
UG471:
7 Series FPGAs SelectIO Resources User Guide.
The maximum limit applied to DC signals.
For maximum undershoot and overshoot AC specifications, see
Table 4.
For soldering guidelines and thermal considerations, see
UG475:
7 Series FPGA Packaging and Pinout Specification.
Description
Min
Max
Units
Storage temperature (ambient)
Maximum soldering temperature for Pb/Sn component bodies
(6)
Maximum soldering temperature for Pb-free component bodies
(6)
Maximum junction temperature
(6)
–65
–
–
–
150
+220
+260
+125
°C
°C
°C
°C
Table 2:
Recommended Operating Conditions
(1)(2)
Symbol
FPGA Logic
V
CCINT
V
CCAUX
V
CCBRAM
V
CCO(3)(4)
V
IN(5)
I
IN(6)
V
CCBATT(7)
Internal supply voltage
For -2L (0.9V) devices: internal supply voltage
Auxiliary supply voltage
Block RAM supply voltage
Supply voltage for 3.3V HR I/O banks
I/O input voltage
I/O input voltage for V
REF
and differential I/O standards
Maximum current through any pin in a powered or unpowered bank
when forward biasing the clamp diode.
Battery voltage
0.95
0.87
1.71
0.95
1.14
–0.20
–0.20
–
1.0
1.00
0.90
1.80
1.00
–
–
–
–
–
1.05
0.93
1.89
1.05
3.465
V
CCO
+ 0.20
2.625
10
1.89
V
V
V
V
V
V
V
mA
V
Description
Min
Typ
Max
Units
GTP Transceiver
V
MGTAVCC(8)(9)
Analog supply voltage for the GTP transmitter and receiver circuits
V
MGTAVTT(8)(9)
Analog supply voltage for the GTP transmitter and receiver termination
circuits
0.97
1.17
1.0
1.2
1.03
1.23
V
V
XADC
V
CCADC
V
REFP
XADC supply relative to GNDADC
Externally supplied reference voltage
1.71
1.20
1.80
1.25
1.89
1.30
V
V
DS181 (v1.5) February 1, 2013
Preliminary Product Specification
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 2:
Recommended Operating Conditions
(1)(2)
(Cont’d)
Symbol
Temperature
Junction temperature operating range for commercial (C) temperature
devices
T
j
Junction temperature operating range for extended (E) temperature
devices
Junction temperature operating range for industrial (I) temperature
devices
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
All voltages are relative to ground.
For the design of the power distribution system consult
UG483,
7 Series FPGAs PCB Design and Pin Planning Guide.
Configuration data is retained even if V
CCO
drops to 0V.
Includes V
CCO
of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
The lower absolute voltage specification always applies.
A total of 200 mA per bank should not be exceeded.
V
CCBATT
is required only when using bitstream encryption. If battery is not used, connect V
CCBATT
to either ground or V
CCAUX
.
Each voltage listed requires the filter circuit described in
UG482:
7 Series FPGAs GTP Transceiver User Guide.
Voltages are specified for the temperature range of T
j
= 0°C to +85°C.
Description
Min
Typ
Max
Units
0
0
–40
–
–
–
85
100
100
°C
°C
°C
Table 3:
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRI
I
REF
I
L
C
IN(2)
Description
Data retention V
CCINT
voltage (below which configuration data might be lost)
Data retention V
CCAUX
voltage (below which configuration data might be lost)
V
REF
leakage current per pin
Input or output leakage current per pin (sample-tested)
Die input capacitance at the pad
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 3.3V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 2.5V
Min
0.75
1.5
–
–
–
90
68
34
23
12
68
45
–
–
28
Typ
(1)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40
Max
–
–
15
15
8
330
250
220
150
120
330
180
25
150
55
Units
V
V
µA
µA
pF
µA
µA
µA
µA
µA
µA
µA
mA
nA
Ω
I
RPU
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.8V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.5V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.2V
Pad pull-down (when selected) @ V
IN
= 3.3V
Pad pull-down (when selected) @ V
IN
= 1.8V
Analog supply current, analog circuits in powered up state
Battery supply current
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_40) for commercial (C), and industrial (I), and extended (E)
temperature devices
I
RPD
I
CCADC
I
BATT(3)
R
IN_TERM
(4)
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_50) for commercial (C), and industrial (I), and extended (E)
temperature devices
Thevenin equivalent resistance of programmable input termination to V
CCO
/2
(UNTUNED_SPLIT_60) for commercial (C), and industrial (I), and extended (E)
temperature devices
35
50
65
Ω
44
60
83
Ω
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Preliminary Product Specification
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 3:
DC Characteristics Over Recommended Operating Conditions
(Cont’d)
Symbol
n
r
Notes:
1.
2.
3.
4.
Typical values are specified at nominal voltage, 25°C.
This measurement represents the die capacitance at the pad, not including the package.
Maximum value specified for worst case process at 25°C.
Termination resistance to a V
CCO
/2 level.
Description
Temperature diode ideality factor
Temperature diode series resistance
Min
–
–
Typ
(1)
1.010
2
Max
–
–
Units
–
Ω
Table 4:
V
IN
Maximum Allowed AC Voltage Overshoot and Undershoot for 3.3V HR I/O Banks
(1)
AC Voltage Overshoot
V
CCO
+ 0.40
V
CCO
+ 0.45
V
CCO
+ 0.50
V
CCO
+ 0.55
V
CCO
+ 0.60
V
CCO
+ 0.65
V
CCO
+ 0.70
V
CCO
+ 0.75
V
CCO
+ 0.80
V
CCO
+ 0.85
V
CCO
+ 0.90
V
CCO
+ 0.95
Notes:
1.
A total of 200 mA per bank should not be exceeded.
% of UI @–40°C to 100°C
100
100
100
100
46.6
21.2
9.75
4.55
2.15
1.02
0.49
0.24
AC Voltage Undershoot
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
–0.75
–0.80
–0.85
–0.90
–0.95
% of UI @–40°C to 100°C
100
61.7
25.8
11.0
4.77
2.10
0.94
0.43
0.20
0.09
0.04
0.02
Table 5:
Typical Quiescent Supply Current
Speed Grade
Symbol
Description
Device
-3
I
CCINTQ
I
CCOQ
I
CCAUXQ
I
CCBRAMQ
Quiescent V
CCINT
supply current
Quiescent V
CCO
supply current
Quiescent V
CCAUX
supply current
Quiescent V
CCBRAM
supply current
XC7A100T
XC7A200T
XC7A100T
XC7A200T
XC7A100T
XC7A200T
XC7A100T
XC7A200T
Notes:
1.
2.
3.
Typical values are specified at nominal voltage, 85°C junction temperature (T
j
) with single-ended SelectIO resources.
Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at
http://www.xilinx.com/power)
to calculate static power consumption for
conditions other than those specified.
1.0V
-2/-2L
155
328
4
5
36
73
4
11
0.9V
-1
155
328
4
5
36
73
4
11
Units
-2L
108
232
4
5
36
73
4
11
mA
mA
mA
mA
mA
mA
mA
mA
155
328
4
5
36
73
4
11
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Preliminary Product Specification
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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Power-On/Off Power Supply Sequencing
The recommended power-on sequence is V
CCINT
, V
CCBRAM
, V
CCAUX
, and V
CCO
to achieve minimum current draw and
ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on
sequence. If V
CCINT
and V
CCBRAM
have the same recommended voltage levels then both can be powered by the same
supply and ramped simultaneously. If V
CCAUX
and V
CCO
have the same recommended voltage levels then both can be
powered by the same supply and ramped simultaneously.
For V
CCO
voltages of 3.3V in HR I/O banks and configuration bank 0:
•
•
The voltage difference between V
CCO
and V
CCAUX
must not exceed 2.625V for longer than T
VCCO2VCCAUX
for each
power-on/off cycle to maintain device reliability levels.
The T
VCCO2VCCAUX
time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTP transceivers is V
CCINT
, V
MGTAVCC
,
V
MGTAVTT
OR V
MGTAVCC
, V
CCINT
, V
MGTAVTT
. There is no recommended sequencing for V
MGTVCCAUX
. Both V
MGTAVCC
and
V
CCINT
can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to
achieve minimum current draw.
If these recommended sequences are not met, current drawn from V
MGTAVTT
can be higher than specifications during
power-up and power-down.
•
When V
MGTAVTT
is powered before V
MGTAVCC
and V
MGTAVTT
– V
MGTAVCC
> 150 mV and V
MGTAVCC
< 0.7V, the
V
MGTAVTT
current draw can increase by 460 mA per transceiver during V
MGTAVCC
ramp up. The duration of the current
draw can be up to 0.3 x T
MGTAVCC
(ramp time from GND to 90% of V
MGTAVCC
). The reverse is true for power-down.
When V
MGTAVTT
is powered before V
CCINT
and V
MGTAVTT
– V
CCINT
> 150 mV and V
CCINT
< 0.7V, the V
MGTAVTT
current
draw can increase by 50 mA per transceiver during V
CCINT
ramp up. The duration of the current draw can be up to
0.3 x T
VCCINT
(ramp time from GND to 90% of V
CCINT
). The reverse is true for power-down.
•
DS181 (v1.5) February 1, 2013
Preliminary Product Specification
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