xr
MAY 2005
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
GENERAL DESCRIPTION
The XR16L2552 (L2552) is a dual universal
asynchronous receiver and transmitter (UART) with 5
volt tolerant inputs. The XR16L2552 is an improved
version of the ST16C2552 UART with lower operating
voltages and 5 volt tolerant inputs. The L2552
provides enhanced UART functions with 16 byte TX
and RX FIFOs, automatic hardware (RTS/CTS) and
software (Xon/Xoff) flow control, and a complete
modem control interface. Onboard status registers
provide the user with error indications and
operational status. Indepedendent programmable
baud rate generators are provided to select transmit
and receive clock rates up to 3.125Mbps. An internal
loop-back capability allows onboard diagnostics. The
L2552 provides block mode data transfers (DMA)
through FIFO controls. DMA transfer monitoring is
provided through the signals TXRDY# and RXRDY#.
An Alternate Function Register provides the user with
the ability to write the control registers for both UARTs
concurrently and selection of the Multi-Function
output (Baudout#, OP2#, or RXRDY#).
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
•
2.25 to 5.5 Volt Operation
•
5 Volt Tolerant Inputs
•
Pin-to-pin and functionally compatible to National
PC16552
•
Pin-to-pin Compatible to Exar’s ST16C2552,
XR16L2752 and XR16C2852 in the 44-PLCC
•
2 Independent UART Channels
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■
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APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16L2552 B
LOCK
D
IAGRAM
Up to 3.125Mbps with external clock of 50 MHz
Register Set Compatible to 16C550
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable RX FIFO Trigger Levels
Automatic RTS/CTS hardware flow control
Automatic XonXoff software flow control
Wireless infrared encoder/decoder
Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
Multi-Function output allows more package
functions with fewer I/O pins
•
Concurrent write to Channels A and B
•
Crystal oscillator or external clock input
•
48-TQFP (7x7x1.0 mm)
and 44-PLCC packages
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDY# A/B
RXRDY# A/B
(48-TQFP Only)
* 5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
8-bit Data
Bus
Interface
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
2.25 to 5.5 Volt VCC
GND
TXA
RXA
TXB
RXB
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
2552BLK
UART Channel B
(same as Channel A)
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
Crystal Osc/Buffer
Modem Control Logic
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Reset
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENTS
xr
REV. 1.1.1
48-TQFP PACKAGE
TXRDYA#
DSRA#
VCC
CTSA#
38
RIA#
CDA#
D2
D1
48
D0
45
43
42
41
40
47
46
44
39
37
NC
D4
D3
D5
D6
D7
A0
XTAL1
GND
XTAL2
RXRDYB#
A1
A2
CHSEL
INTB
1
2
3
4
5
6
7
8
9
10
11
12
15
13
18
19
20
22
14
16
17
21
23
24
36
35
34
33
RXA
TXA
DTRA#
RTSA#
MFA#
RXRDYA#
INTA
VCC
TXRDYB#
RIB#
CDB#
DSRB#
XR16L2552
48-pin TQFP
32
31
30
29
28
27
26
25
44-PLCC PACKAGE
TXRDYA#
DSRA#
41
CTSA#
40
CDA#
42
RIA#
43
IOR#
RXB
TXB
RTSB#
RESET
DTRB#
CTSB#
MFB#
IOW#
GND
CS#
D5
D6
D7
A0
XTAL1
7
8
9
10
11
44
6
5
4
3
2
1
VCC
NC
D4
D3
D2
D1
D0
39
38
37
36
RXA
TXA
DTRA#
RTSA#
GND 12
XTAL2
A1
13
14
XR16L2552
44-pin PLCC
35 MFA#
34
33
32
31
INTA
VCC
TXRDYB#
RIB#
A2 15
CHSEL 16
INTB
17
CS# 18
MFB# 19
IOW# 20
RESET 21
GND 22
RTSB# 23
IOR# 24
RXB 25
TXB 26
DTRB# 27
CTSB# 28
30 CDB#
29
DSRB#
ORDERING INFORMATION
P
ART
N
UMBER
XR16L2552IM
XR16L2552IJ
P
ACKAGE
48-Lead TQFP
44-Lead PLCC
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
2
xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
N
AME
48-TQFP 44-PLCC
T
YPE
P
IN
#
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
10
9
4
3
2
1
48
47
46
45
44
20
15
14
10
9
8
7
6
5
4
3
2
24
I
Address data lines [2:0]. These 3 address lines select one of the internal reg-
isters in UART channel A/B during a data bus transaction.
I/O
Data bus lines [7:0] (bidirectional).
I
Input/Output Read Strobe (active low). The falling edge instigates an internal
read cycle and retrieves the data byte from an internal register pointed to by
the address lines [A2:A0]. The data byte is placed on the data bus to allow the
host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an internal
write cycle and the rising edge transfers the data byte on the data bus to an
internal register pointed by the address lines.
UART chip select (active low). This function selects channel A or B in accor-
dance with the logical state of the CHSEL pin. This allows data to be trans-
ferred between the user CPU and the L2552.
Channel Select - UART channel A or B is selected by the logical state of this
pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART
channel B while a logic 1 selects UART channel A. Normally, CHSEL could
just be an address line from the user CPU such as A3. Bit-0 of the Alternate
Function Register (AFR) can temporarily override CHSEL function, allowing
the user to write to both channel register simultaneously with one write cycle
when CS# is low. It is especially useful during the initialization routine.
UART channel A Interrupt output (active high). A logic high indicates channel
A is requesting for service.
UART channel B Interrupt output (active high). A logic high indicates channel
B is requesting for service.
UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A. If it is not used, leave it uncon-
nected.
UART channel A Receiver Ready (active low). This output provides the RX
FIFO/RHR status for receive channel A. This pin is only available on the 48-
pin TQFP package. If it is not used, leave it unconnected.
UART channel B Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel B. If it is not used, leave it uncon-
nected.
IOW#
15
20
I
CS#
13
18
I
CHSEL
11
16
I
INTA
INTB
TXRDYA#
30
12
43
34
17
1
O
O
O
RXRDYA#
31
-
O
TXRDYB#
28
32
O
3
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
Pin Description
N
AME
RXRDYB#
48-TQFP 44-PLCC
T
YPE
P
IN
#
P
IN
#
8
-
O
D
ESCRIPTION
xr
REV. 1.1.1
UART channel B Receiver Ready (active low). This output provides the RX
FIFO/RHR status for receive channel B. This pin is only available on the 48-
pin TQFP package. If it is not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
RXA
RTSA#
35
36
33
38
39
36
O
I
O
UART channel A Transmit Data. If it is not used, leave it unconnected.
UART channel A Receive Data. Normal receive data input must idle at logic 1
condition. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control, see EFR[6],
MCR[1] and IER[6]. If it is not used, leave it unconnected.
UART channel A Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7] and IER[7]. This input should
be connected to VCC when not used.
UART channel A Data-Terminal-Ready (active low) or general purpose output.
If it is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
UART channel A Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
UART channel A Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
UART channel B Transmit Data. If it is not used, leave it unconnected.
UART channel B Receive Data. Normal receive data input must idle at logic 1
condition. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor.
UART channel B Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control, see EFR[6],
MCR[1] and IER[6]. If it is not used, leave it unconnected.
UART channel B Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7] and IER[7]. This input should
be connected to VCC when not used.
UART channel B Data-Terminal-Ready (active low) or general purpose output.
If it is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
UART channel B Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
CTSA#
38
40
I
DTRA#
DSRA#
34
39
37
41
O
I
CDA#
40
42
I
RIA#
41
43
I
TXB
RXB
RTSB#
22
21
18
26
25
23
O
I
O
CTSB#
24
28
I
DTRB#
DSRB#
23
25
27
29
O
I
CDB#
26
30
I
4
xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
Pin Description
N
AME
RIB#
48-TQFP 44-PLCC
T
YPE
P
IN
#
P
IN
#
27
31
I
D
ESCRIPTION
UART channel B Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
Multi-Function Output Channel A. This output pin can function as the OP2A#,
BAUDOUTA#, or RXRDYA# pin. One of these output signal functions can be
selected by the user programmable bits 1-2 of the Alternate Function Register
(AFR). These signal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is a logic 0
when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a
logic 1 condition after a reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate
clock output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data
transfers. If using the 48-TQFP package, this output is already available at pin
31.
If it is not used, leave it unconnected.
MFB#
14
19
O
Multi-Function Output ChannelB. This output pin can function as the OP2B#,
BAUDOUTB#, or RXRDYB# pin. One of these output signal functions can be
selected by the user programmable bits 1-2 of the Alternate Function Register
(AFR). These signal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is a logic 0
when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a
logic 1 condition after a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate
clock output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data
transfers. If using the 48-TQFP package, this output is already available at pin
8.
If it is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
5
7
16
11
13
21
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the
internal registers and all outputs. The UART transmitter output will be held at
logic 1, the receiver input will be ignored and outputs are reset during reset
period (see External Reset Conditions).
MFA#
32
35
O
VCC
GND
29, 42
6, 17
44, 33
22, 12
Pwr 2.25V to 5.5V power supply. All input pins are 5V tolerant.
Pwr Power supply common, ground.
5
