áç
AUGUST 2003
DISCONTINUED
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
GENERAL DESCRIPTION
The XR17L154
1
(L154) is a quad PCI Bus Universal
Asynchronous Receiver and Transmitter (UART) with
same package and pin-out as the Exar XR17C158
octal UART. The device is designed to meet today’s
32-bit PCI Bus and high bandwidth requirement in
communication systems. The global interrupt source
register provides a complete interrupt status
indication for all 4 channels to speed up interrupt
parsing. Each UART is independently controlled and
has its own 16C550 compatible 5G register set,
transmit and receive FIFOs of 64 bytes, fully
programmable transmit and receive FIFO trigger
levels, transmit and receive FIFO level counters,
automatic hardware flow control with programmable
hysteresis, automatic software (Xon/Xoff) flow
control, IrDA (Infrared Data Association) encoder/
decoder, 8 multi-purpose definable inputs/outputs,
and a 16-bit general purpose timer/counter.
N
OTE
:
1 Covered by U.S. Patents #5,649,122, #5,949,787
FEATURES
APPLICATIONS
•
High Performance Quad UART
•
PCI Bus 2.2 Target Interface Compliance
•
3.3 Volt PCI Bus Compliant up to 33 MHz Clock
•
5 Volt Tolerant Serial Inputs
•
32-bit PCI Bus Interface with EEPROM Interface
•
A Global Interrupt Source Register for all 4 UARTs
•
Data Transfer in Byte, Word and Double-word
•
Data Read/Write Burst Operation
•
Each UART is independently Controlled with:
•
16C550 Compatible 5G (Fifth Gen) Register Set
•
64-byte Transmit and Receive FIFOs
•
Transmit and Receive FIFO Level Counters
•
Automatic RTS/CTS or DTR/DSR Flow Control
•
Automatic Xon/Xoff Software Flow Control
•
Automatic RS485 Half-duplex Control Output with
Selectable Turn-around Delay (0 to 15 bit-times)
•
Infrared (IrDA 1.0) Data Encoder/Decoder
•
Remote Access Servers
•
Ethernet Network to Serial Ports
•
Network Management
•
Factory Automation and Process Control
•
Point-of-Sale Systems
•
Multi-port RS-232/RS-422/RS-485 Cards
•
Eight Multi-Purpose Inputs/outputs
•
General Purpose 16-bit Timer/Counter
•
Sleep Mode with Automatic Wake-up
•
Same Package and Pin-out as the XR17C158,
XR17D158, XR17C154 and XR17D154 UARTs
•
Programmable Data Rate with Prescaler
•
Up to 4 Mbps Serial Data Rate at 8X
F
IGURE
1. B
LOCK
D
IAGRAM
*5V Tolerance for non-PCI Inputs
CLK (33MHz)
RST#
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
INTA#
IDSEL
PERR#
SERR#
PAR
UART Channel 0
64 Byte TX FIFO
UART
Regs
TX & RX
IR
ENDEC
3.3V VCC
GND
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
PCI Local
Bus
Interface
Device
Configuration
Registers
BRG
64 Byte RX FIFO
UART Channel 1
UART Channel 2
Configuration
Space
Registers
TX3, RX3, DTR3#,
DSR3#, RTS3#,
CTS3#, CD3#, RI3#
UART Channel 3
EECK
EEDI
EEDO
EECS
ENIR
EEPROM
Interface
16-bit
Timer/Counter
Multi-purpose
.
Inputs/Outputs
Crystal Osc/Buffer
MPIO0- MPIO7
XTAL1
XTAL2
TMRCK
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
áç
DISCONTINUED
F
IGURE
2. P
IN
O
UT OF THE
D
EVICE
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
DTR1#
101 DSR1#
104 RTS1#
100 CTS1#
108 MPIO0
107 MPIO1
87 DTR2#
CD1#
DSR2#
RTS2#
CD2#
CTS2#
VCC
103 RI1#
RI2#
RX1
TX2
106
TX1
105
102
99
98
97
96
95
94
93
92
91
90
89
88
86
85
84
83
82
81
80
79
78
77
76
75
74
MPIO2
GND
XTAL2
XTAL1
TEST#
VCC
EEDO
EEDI
EECS
EECK
NC
NC
NC
NC
NC
NC
NC
NC
TX0
DTR0#
RTS0#
RI0#
CD0#
DSR0#
CTS0#
RX0
INTA#
RST#
CLK
GND
VI/O
AD31
AD30
AD29
AD28
AD27
AD26
AD25
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
MPIO3
RX2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
31
27
32
33
34
35
DEVSEL# 18
19
20
21
24
CBE1 25
28
29
11
12
17
PERR# 22
FRAME# 15
SERR# 23
10
13
CBE2 14
16
26
30
36
2
4
1
5
3
6
7
8
9
NC
NC
ENIR
TMRCK
MPIO4
MPIO5
MPIO6
MPIO7
VCC
GND
TX3
DTR3#
RTS3#
RI3#
CD3#
DSR3#
CTS3#
RX3
NC
NC
NC
NC
NC
NC
NC
NC
GND
VI/O
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
XR17L154
144-TQFP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
CBE3
IDSEL
STOP#
TRDY#
AD22
AD19
AD16
AD14
AD13
AD12
AD21
AD18
AD11
IRDY#
ORDERING INFORMATION
O
PERATING
P
ART
N
UMBER
XR17L154CV
XR17L154IV
P
ACKAGE
144-Lead TQFP
144-Lead TQFP
T
EMPERATURE
R
ANGE
0°C to +70°C
-40°C to +85°C
D
EVICE
S
TATUS
Discontinued. See XR17D154CV for a replacement.
Discontinued. See XR17D154IV for a replacement.
2
CBE0
AD24
AD23
AD20
AD17
AD15
AD10
GND
GND
VI/O
AD9
AD8
GND
VI/O
PAR
VI/O
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
áç
DISCONTINUED
PIN DESCRIPTIONS
N
AME
P
IN
#
T
YPE
D
ESCRIPTION
PCI LOCAL BUS INTERFACE
RST#
134
I
Bus reset input (active low). It resets the PCI local bus configuration space
registers, device configuration registers and UART channel registers to the
default condition, see
Table 18
.
Bus clock input of up to 33MHz at 3.3V.
Address data lines [31:0] (bidirectional).
CLK
AD31-AD0
135
138-144,
1, 6-13
26-33
37-44
15
2,14,25,36
I
IO
FRAME#
C/BE3#
-
C/BE0#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
INTA#
PAR
PERR#
SERR#
I
I
Bus transaction cycle frame (active low). It indicates the beginning and dura-
tion of an access.
Bus Command/Byte Enable [3:0] (active low). This line is multiplexed for bus
Command during the address phase and Byte Enable during the data phase.
Initiator Ready (active low). During a write, it indicates valid data is present on
data bus. During a read, it indicates the master is ready to accept data.
Target Ready (active low).
Target request to stop current transaction (active low). 5
Initialization device select (active high).
Device select to the XR17L154 (active low).
Device interrupt from XR17L154 (open drain, active low).
Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active high).
Parity error indicator to host (active low). Optional in bus target application.
System error indicator to host (open drain, active low). Optional in bus target
application.
16
17
21
3
18
133
24
22
23
I
O
O
I
O
OD
IO
O
OD
MODEM OR SERIAL I/O INTERFACE
TX0
RX0
125
132
O
I
UART channel 0 Transmit Data or infrared transmit data.
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
UART channel 0 Request to Send or general purpose output (active low).
UART channel 0 Clear to Send or general purpose input (active low).
UART channel 0 Data Terminal Ready or general purpose output (active low).
UART channel 0 Data Set Ready or general purpose input (active low).
UART channel 0
Carrier Detect or general purpose input (active low).
UART channel 0 Ring Indicator or general purpose input (active low).
UART channel 1 Transmit Data or infrared transmit data.
RTS0#
CTS0#
DTR0#
DSR0#
CD0#
RI0#
TX1
127
131
126
130
129
128
106
O
I
O
I
I
I
O
3
áç
DISCONTINUED
PIN DESCRIPTIONS
N
AME
RX1
P
IN
#
99
T
YPE
I
D
ESCRIPTION
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
UART channel 1 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
UART channel 1 Request to Send or general purpose output (active low).
UART channel 1 Clear to Send or general purpose input (active low).
UART channel 1 Data Terminal Ready or general purpose output (active low).
UART channel 1 Data Set Ready or general purpose input (active low).
UART channel 1 Carrier Detect or general purpose input (active low).
UART channel 1 Ring Indicator or general purpose input (active low).
UART channel 2 Transmit Data or infrared transmit data.
UART channel 2 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
UART channel 2 Request to Send or general purpose output (active low).
UART channel 2 Clear to Send or general purpose input (active low).
UART channel 2 Data Terminal Ready or general purpose output (active low).
UART channel 2 Data Set Ready or general purpose input (active low).
UART channel 2
Carrier Detect or general purpose input (active low).
UART channel 2 Ring Indicator or general purpose input (active low).
UART channel 3 Transmit Data or infrared transmit data.
UART channel 3 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
UART channel 3 Request to Send or general purpose output (active low).
UART channel 3 Clear to Send or general purpose input (active low).d.
UART channel 3 Data Terminal Ready or general purpose output (active low).
UART channel 3 Data Set Ready or general purpose input (active low).
UART channel 3
Carrier Detect or general purpose input (active low).
UART channel 3 Ring Indicator or general purpose input (active low).
RTS1#
CTS1#
DTR1#
DSR1#
CD1#
RI1#
TX2
RX2
104
100
105
101
102
103
88
81
O
I
O
I
I
I
O
I
RTS2#
CTS2#
DTR2#
DSR2#
CD2#
RI2#
TX3
RX3
86
82
87
83
84
85
62
55
O
I
O
I
I
I
O
I
RTS3#
CTS3#
DTR3#
DSR3#
CD3#
RI3#
60
56
61
57
58
59
O
I
O
I
I
I
ANCILLARY SIGNALS
MPIO0
MPIO1
MPIO2
108
107
74
I/O
I/O
I/O
Multi-purpose input/output 0. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
Multi-purpose input/output 1. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 2. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
4
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
áç
DISCONTINUED
T
YPE
I/O
I/O
I/O
I/O
I/O
O
D
ESCRIPTION
Multi-purpose input/output 3. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 4. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 5. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 6. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 7. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Serial clock to EEPROM. Pin has a weak internal pull-down resistor and
requires an external 10K resistor to operate correctly with the EEPROM. An
internal clock of CLK divide by 256 is used for reading the vendor and sub-
vendor ID and model number during power up or reset. However, it can be
manually clocked thru the Configuration Register REGB.
Chip select to a EEPROM device like 93C46. It is manually selectable thru the
Configuration Register REGB. Requires a pull-up 4.7KΩ resistor for external
sensing of EEPROM during power up. See DAN112 for further details.
Write data to EEPROM device. It is manually accessible thru the Configura-
tion Register REGB. The L154 auto-configuration register interface logic uses
the 16-bit format.
Read data from EEPROM device. It is manually accessible thru the Configu-
ration Register REGB.
Crystal or external clock input of up to 33MHz for 2Mbps at 3.3V. Caution:
This input is not 5V tolerant.
Crystal or buffered clock output.
16-bit timer/counter external clock input.
Infrared mode enable (active high). Start up all 4 UARTs in infrared mode
upon power up or reset.
Factory Test. Connect to VCC for normal operation.
5V or 3.3V power supply for the core logic.
PCI bus I/O power supply. 3.3V ONLY (PCI 2.2 Compliance).
Power supply common, ground.
PIN DESCRIPTIONS
N
AME
MPIO3
MPIO4
MPIO5
MPIO6
MPIO7
EECK
P
IN
#
73
68
67
66
65
116
EECS
115
O
EEDI
114
O
EEDO
XTAL1
XTAL2
TMRCK
ENIR
TEST#
VCC
VI/O
GND
113
110
109
69
70
111
64, 90, 112
4, 19, 34, 45, 137
5,20,35,46,63,
89,136
47-54, 71, 72,
75-80, 91-98,
117-124
I
I
O
I
I
I
PWR
PWR
PWR
NC
No Connection. These pins are reserved and used by the octal PCI UART
XR17C158.
N
OTE
:
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
5
