DATASHEET
ZL9006M
Digital DC/DC PMBus 6A Power Module
The
ZL9006M
is a 6A adjustable output, step-down synchronous
PMBus-compliant digital power supply. Included in the module
is a high-performance digital PWM controller, power MOSFETs,
an inductor, and all the passive components required for a
highly integrated DC/DC power solution. This power module has
built-in auto compensation algorithms, which eliminates the
need for manual compensation design work. The ZL9006M
operates over a wide input voltage range and supports an
output voltage range of 0.6V to 3.6V, which can be set by
external resistors or via PMBus. Only bulk input and output
capacitors are needed to finish the design. The output voltage
can be precisely regulated to as low as 0.6V with ±1% output
voltage regulation over line, load and temperature variations.
The ZL9006M functions as a switch mode power supply with
added benefits of auto compensation, programmable power
management features, parametric monitoring, and status
reporting capabilities.
The ZL9006M is packaged in a thermally enhanced, compact
(17.2mmx11.45mm) and low profile (2.5mm) overmolded
High-Density Array (HDA) package module suitable for
automated assembly by standard surface mount equipment.
The ZL9006M is RoHS compliant.
Figure 1
represents a typical implementation of the ZL9006M.
For PMBus operation, it is recommended to tie the Enable pin
(EN) to SGND.
FN7959
Rev 2.00
March 16, 2016
Features
• Complete digital switch mode power supply
• Auto compensating PID filter
• ±1% output voltage accuracy
• External synchronization
• Overcurrent/undercurrent protection
• Output voltage tracking
• Phase interleaving
• Programmable sequencing (delay and ramp time)
•
Snapshot™
parametric capture
• PMBus compliant
Applications
• Server, telecom, and datacom
• Industrial and medical equipment
• General purpose point of load
V
IN
4.5V TO
13.2V
DGND
POWER-GOOD
OUTPUT
ENABLE
EXT SYNC
DDC BUS
PG
EN
SYNC
DDC
SCL
PMBus
VDD
2x22µF
16V
VIN
V
OUT
VOUT
ZL9006M
C
OUT
PGND
SGND
FB+
FB-
V1
2.5mm
SDA
SA
m
45m
11.
R
SA
m
17.2
m
R
SET
*Patent pending package
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FIGURE 2. SMALL FOOTPRINT PACKAGE
WITH LOW PROFILE AT 2.5mm
FN7959 Rev 2.00
March 16, 2016
Page 1 of 69
ZL9006M
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinout Internal Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Derating and Power Loss Curves . . . . . . . . . . . . . . . . . . . . . 11
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Internal Bias and Input Voltage Considerations . . . . . . . . . . 12
Preprogramming Configuration . . . . . . . . . . . . . . . . . . . . . . . . 12
Design Trade-Offs with Switching Frequency . . . . . . . . . . . . . 13
Completing a Power Supply Design . . . . . . . . . . . . . . . . . . . . 13
Selection of the Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . 13
Selection of the Output Capacitors . . . . . . . . . . . . . . . . . . . . . 13
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PMBus Module Address Selection. . . . . . . . . . . . . . . . . . . . . . 14
Phase Spreading for a Single-Phase Mode of Operation . . . 15
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Start-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Soft-Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . 17
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . 18
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Adaptive Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Tracking Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Monitoring Via PMBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . 24
SnapShot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . 24
Nonvolatile Memory and Device Security Features. . . . . . . . 25
Layout Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PMBus™ Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PMBus Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PMBus Commands Description . . . . . . . . . . . . . . . . . . . . . . .32
Firmware Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
FN7959 Rev 2.00
March 16, 2016
Page 2 of 69
ZL9006M
Pin Configuration
ZL9006M
(32 LD HDA)
TOP VIEW
XTEMP
DDC
VDD
7
VDD
8
9
V25
V25
PG
3
EN
4
1
A
B
2
5
6
10 11 12 13 14 15 16 17
PAD1
VIN
V25
V25
SGND C
DGND D
SYNC E
SA F
SCL G
SDA H
SALRT J
FC0 K
L
1
V1
2
V1
PAD3
SGND
PGND
PAD4
SW
VR
PAD5
VOUT
3
SS
4
VTRK
5
6
FB+
7
FB-
8
ISENB
9
10 11 12 13 14 15 16 17
Pin Descriptions
PIN
A1, A2,
B3, B6
A3
A4
LABEL
V25
PG
EN
TYPE
PWR
0
I
DESCRIPTION
Internal 2.5V reference. It is used to power internal circuitry.
Power-good output. Provide open-drain power-good signal. By default, the PG pin asserts if the output is within
+15/-10% of the target voltage. These limits and the polarity of the pin may be changed via the PMBus interface.
Enable input. This pin is factory set as active high. Pull-up to enable the module switching and pull-down to disable
switching. If the module is controlled through PMBus command, tie a 10kΩ resistor from this pin to SGND to avoid this
pin floating.
Digital-DC bus (open drain). The DDC pin on all Digital modules in one application should be connected together. This
dedicated bus provides the communication channel between modules for features such as sequencing, fault spreading,
and current sharing. A pull-up resistor is required for this application.
External temperature sensor input. Connect to an external 2N3904 transistor with a diode configuration (see
Figure 25
on page 24).
Controller input voltage. Tie to VIN directly.
Signal ground. Connect to low impedance ground plane. Refer to
“Layout Guide” on page 25.
Digital ground. Common return for digital signals. Connect to low impedance ground plane. Refer to
“Layout Guide” on
page 25.
Clock synchronization. Used for synchronization to external frequency reference and for setting switching frequency.
Refer to
Table 7 on page 17.
Serial address select pin. Used to assign unique PMBus address to each module and phase spreading.
Power ground. Connect to low impedance ground plane.
Serial clock. PMBus interface pin.
Serial data. PMBus interface pin.
Internal 5V reference. Used to power internal drivers. The current limit for the VR pin is 10mA. Please consider this when
using the VR pin for driving external circuitry.
Serial alert. PMBus interface pin.
A5
DDC
I/O
A6
A7, A8
C1
D1
E1
F1
F10
G1
H1
H9
J1
XTEMP
VDD
SGND
DGND
SYNC
SA
PGND
SCL
SDA
VR
SALRT
I
PWR
PWR
PWR
I/O
I
PWR
I/O
I/O
PWR
O
FN7959 Rev 2.00
March 16, 2016
PAD2
PGND
Page 3 of 69
ZL9006M
Pin Descriptions
PIN
K1
L1, L2
LABEL
FC0
V1
TYPE
I
I
(Continued)
DESCRIPTION
Mode Setting. Used to set the single-phase/current sharing mode, auto compensation, and SYNC configuration (see
Table 9 on page 19).
Output voltage selection pin. Used to program the output voltage through pin-strap setting or connecting a resistor from the
V1 pin to SGND (see
Table 4 on page 15).
The set voltage on this pin is the maximum allowed output voltage in PMBus
programming.
Soft-start pin. Set SS pin by pin-strapping or connecting a resistor to SGND using the appropriate resistor. The pin can program
the delay from when EN is asserted until the output voltage starts to ramp, the output voltage ramp time during turn
on/off, and input undervoltage lockout (UVLO) level (see
Table on page 17).
This pin can also
set tracking ratio and upper
track limit (see
Table 10 on page 21).
Tracking sense input. Used to track an external voltage source.
Output voltage positive feedback. Positive inputs of differential remote sense for the regulator. Connect to the output
rail or the regulation point of load/processor. This pin is noise sensitive. Please refer to
“Layout Guide” on page 25.
Output voltage negative feedback. Negative input of the differential remote sense for the regulator. Connect to the
negative rail or ground of the load/processor.
Test pin. For factory test use. Solder down the pin for mechanical strength, but do not connect the pin.
Power inputs. Input voltage range: 4.5V to 13.2V. Tie directly to the input rail. When the input is between 4.5V to 5.5V,
VIN should be tied directly to VCC.
Power ground. Power ground pins for both input and output returns.
Signal ground. Connect to low impedance ground plane (see
Figure 26 on page 25).
Switch node. Use for monitoring switching frequency. SW pad should be floating or used for snubber connections. To
achieve better thermal performance, the SW planes can also be used for heat removal with thermal vias connected to
large inner layers (see
Figure 26 on page 25).
Power Output. Apply output load between these pins and PGND pins. Output voltage range: 0.6V to 3.6V.
L3
SS
I
L4
L6
L7
L8
PAD1
PAD2
PAD3
PAD4
VTRK
FB+
FB-
ISENB
VIN
PGND
SGND
SW
I
I
I
TEST
PWR
PWR
PWR
PWR
PAD5
VOUT
PWR
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ZL9006MIRZ
ZL9006MAIRZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil plastic packaged products are RoHS compliant by EU exemption 7C-I and employ special Pb-free material sets; molding compounds/die
attach materials and NiPdAu plate - e4 termination finish which is compatible with both SnPb and Pb-free soldering operations. Intersil RoHS
compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ZL9006M.
For more information on MSL please see Tech Brief
TB363.
4. See
“Firmware Revision History” on page 64;
only the latest firmware revision is recommended for new designs.
PART
MARKING
ZL9006M
ZL9006M
FIRMWARE REVISION
(Note
4)
FE03
FE04
TEMP RANGE
(°C)
-40 to +85
-40 to +85
PACKAGE
(RoHS Compliant)
32 Ld 17.2x11.45 HDA
32 Ld 17.2x11.45 HDA
PKG.
DWG. #
Y32.17.2x11.45
Y32.17.2x11.45
ZL
DIGITAL MODULE DESIGNATOR
BASE PART NUMBER
FIRMWARE REVISION
BLANK: FE03
A: FE04
xxxxM
F
T
R
Z
S
SHIPPING OPTION
BLANK: BULK
T: TAPE AND REEL
RoHS
Z: RoHS COMPLIANT
OPERATING TEMPERATURE
I: INDUSTRIAL (‐ 40°C TO +85°C)
PACKAGE DESIGNATOR
R: QUAD FLAT NO‐LEAD (QFN)
FN7959 Rev 2.00
March 16, 2016
Page 4 of 69
ZL9006M
Pinout Internal Circuit
PG
A3
EN
A4
FC0 SS VTRK V1
K1
L3
L4
L1
V1
L2
VDD VDD
A7
A8
VR
H9
V25
A1
V25 V25
A2
B3
V25
B6
VIN
Pad 1
14
3
L
FILTER
LDO
LDO
2µF
SS
MGN
OV/UV POWER MANAGEMENT
OC/UC
CURRENT SHARE
INTERLEAVE
AUTOCOMP
VCC
GATE DRIVE LOGIC
SYNC
OUT
GH
PWMH
Pad 4
SW
SYNC
E1
PLL
D-PWM
1.0µH
PWML
GATE DRIVER
14
Pad 5
VOUT
NVM
10µF
GL
GND
SUPERVISOR
NLR
DIGITAL
COMPENSATOR
PROTECTION
CSA
L8
ISENB
VOUT
22
L6
SCL
SDA
SALRT
SA
DDC
G1
H1
J1
ADC
COMMUNICATION
ADC
VSA
VDD
TEMP
SENSOR
A6
L7
FB+
FB-
22
F1
A5
SGND
DGND
DIGITAL CONTROLLER
XTEMP
D1
F10
Pad 2
14
Pad 3
14
C1
DGND
PGND
PGND
SGND
SGND
FN7959 Rev 2.00
March 16, 2016
Page 5 of 69
