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ispGAL22V10AV-23LS

SPLD - Simple Programmable Logic Devices 23 INPUT 10 OUTPUT 3.3V ispJTAG 2.3ns

器件类别：可编程逻辑器件    可编程逻辑   

厂商名称：Lattice(莱迪斯)

厂商官网：http://www.latticesemi.com

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Lattice(莱迪斯)
零件包装代码
QFN
包装说明
5 X 5 MM, QFN-32
针数
32
Reach Compliance Code
compliant
ECCN代码
EAR99
Is Samacsys
N
架构
PAL-TYPE
最大时钟频率
303 MHz
JESD-30 代码
S-XQCC-N32
长度
5 mm
湿度敏感等级
1
专用输入次数
11
I/O 线路数量
10
输入次数
22
输出次数
10
产品条款数
132
端子数量
32
组织
11 DEDICATED INPUTS, 10 I/O
输出函数
MACROCELL
封装主体材料
UNSPECIFIED
封装代码
HVQCCN
封装等效代码
LCC32,.2SQ,20
封装形状
SQUARE
封装形式
CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
电源
3.3 V
可编程逻辑类型
EE PLD
传播延迟
2.3 ns
认证状态
Not Qualified
座面最大高度
1 mm
最大供电电压
3.6 V
最小供电电压
3 V
标称供电电压
3.3 V
表面贴装
YES
技术
CMOS
端子形式
NO LEAD
端子节距
0.5 mm
端子位置
QUAD
宽度
5 mm
Base Number Matches
1
文档预览
GAL
®
22LV10 Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
GAL22LV10C
GAL22LV10D
Ordering Part Number
GAL22LV10C-7LJ
GAL22LV10C-7LJN
GAL22LV10C-10LJ
GAL22LV10C-10LJN
GAL22LV10C-15LJ
GAL22LV10C-15LJN
GAL22LV10D-4LJ
GAL22LV10D-4LJN
GAL22LV10D-5LJ
GAL22LV10D-5LJN
Product Status
Reference PCN
PCN#06-07
Discontinued
PCN#09-10
Discontinued
PCN#09-10
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
Ne
Tolew 5V
Inp rant
22Luts on
V10
D
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices
(GAL22LV10C)
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
GAL22LV10
Low Voltage E
2
CMOS PLD
Generic Array Logic™
Functional Block Diagram
I/CLK
RESET
8
OLMC
I/O/Q
I
10
OLMC
PROGRAMMABLE
AND-ARRAY
(132X44)
• ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• LEAD-FREE PACKAGE OPTIONS
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL22LV10D, at 4 ns maximum propagation delay time, pro-
vides the highest speed performance available in the PLD market.
The GAL22LV10C can interface with both 3.3V and 5V signal levels.
The GAL22LV10 is manufactured using Lattice Semiconductor's
advanced 3.3V E
2
CMOS process, which combines CMOS with
Electrically Erasable (E
2
) floating gate technology. High speed erase
times (<100ms) allow the devices to be reprogrammed quickly and
efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
GND
Copyright © 2008 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
I/O/Q
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
I
I
NC
I
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
22lv10_07
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
I
12
I/O/Q
I
OLMC
I/O/Q
14
I
OLMC
I/O/Q
16
I
OLMC
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
PRESET
Description
Pin Configuration
PLCC
NC
I/CLK
I/O/Q
I
4
2
28
Vcc
I
26
I
I
I
5
I/O/Q
25
I/O/Q
I/O/Q
I/O/Q
NC
7
NC
GAL22LV10
Top View
23
I
I
I
9
21
I/O/Q
I/O/Q
11
12
14
16
19
18
I/O/Q
August 2008
1
Specifications
GAL22LV10
GAL22LV10 Ordering Information
Conventional Packaging
Commercial Grade Specifications
Tpd (ns)
4
5
7.5
10
15
Tsu (ns)
3
3.5
6.5
7.5
10
Tco (ns)
3
3.5
5
6. 5
10
Icc (mA)
130
130
75
75
75
Ordering #
GAL22LV10D-4LJ
GAL22LV10D-5LJ
GAL22LV10C-7LJ
1
GAL22LV10C-10LJ
GAL22LV10C-15LJ
Package
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
Lead-Free Packaging
Commercial Grade Specifications
Tpd (ns)
4
5
Tsu (ns)
3
3.5
Tco (ns)
3
3.5
5
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Icc (mA)
130
75
130
75
Ordering #
Package
GAL22LV10D-4LJN
Lead-Free 28-Lead PLCC
GAL22LV10D-5LJN
Lead-Free 28-Lead PLCC
7.5
10
15
6.5
10
GAL22LV10C-7LJN
1
Lead-Free 28-Lead PLCC
7.5
6.5
10
GAL22LV10C-10LJN
Lead-Free 28-Lead PLCC
75
GAL22LV10C-15LJN
Lead-Free 28-Lead PLCC
Part Number Description
XXXXXXXX _ XX
X
X X
GAL22LV10D
Device Name
GAL22LV10C
Speed (ns)
Grade
Blank = Commercial
L = Low Power
Power
Package
J = PLCC
JN =
Lead-Free PLCC
2
Specifications
GAL22LV10
Output Logic Macrocell (OLMC)
The GAL22LV10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 17 and 27), two have ten product terms
(pins 18 and 26), two have twelve product terms (pins 19 and 25),
two have fourteen product terms (pins 20 and 24), and two OLMCs
have sixteen product terms (pins 21 and 23). In addition to the
product terms available for logic, each OLMC has an additional
product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
The GAL22LV10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
Each of the Macrocells of the GAL22LV10 has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (SO and S1), which are nor-
mally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
A R
D
Q
4 TO 1
MUX
CLK
Q
SP
2 TO 1
MUX
GAL22LV10 OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
3
Specifications
GAL22LV10
Registered Mode
AR
AR
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
CLK
Q
CLK
Q
D
Q
D
Q
SP
SP
ACTIVE LOW
ACTIVE HIGH
S
0
= 0
S
1
= 0
S
0
= 1
S
1
= 0
Combinatorial Mode
ACTIVE LOW
ACTIVE HIGH
S
0
= 0
S
1
= 1
S
0
= 1
S
1
= 1
4
查看更多>
参数对比
与ispGAL22V10AV-23LS相近的元器件有：GAL22LV10C-7LJ、GAL22LV10C-15LJN、GAL22LV10D-4LJ、ispGAL22V10AB-5LSI、GAL22LV10C-15LJ、ispGAL22V10AV-5LSN、ispGAL22V10AB-75LS、GP6548-2640-CB、GAL22LV10D-5LJN。描述及对比如下：
型号 ispGAL22V10AV-23LS GAL22LV10C-7LJ GAL22LV10C-15LJN GAL22LV10D-4LJ ispGAL22V10AB-5LSI GAL22LV10C-15LJ ispGAL22V10AV-5LSN ispGAL22V10AB-75LS GP6548-2640-CB GAL22LV10D-5LJN
描述 SPLD - Simple Programmable Logic Devices 23 INPUT 10 OUTPUT 3.3V ispJTAG 2.3ns SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD SPLD - Simple Programmable Logic Devices 59 INPUT 10 OUTPUT 3.3V ispJTAG 2.3ns SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD SPLD - Simple Programmable Logic Devices 31 INPUT 10 OUTPUT 3.3V ispJTAG 2.3ns SPLD - Simple Programmable Logic Devices 56 INPUT 10 OUTPUT 3.3V ispJTAG 2.3ns Fixed Resistor, Metal Film, 1W, 264ohm, 400V, 0.25% +/-Tol, 100ppm/Cel, SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD
Reach Compliance Code compliant unknown unknown unknown compliant unknown unknown compliant compliant unknown
端子数量 32 28 28 28 32 28 32 32 2 28
封装形状 SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE CYLINDRICAL PACKAGE SQUARE
封装形式 CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE Axial CHIP CARRIER
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS METAL FILM CMOS
是否Rohs认证 不符合 不符合 符合 不符合 不符合 不符合 符合 不符合 - 符合
零件包装代码 QFN QLCC QLCC QLCC QFN QLCC QFN QFN - QLCC
包装说明 5 X 5 MM, QFN-32 PLASTIC, LCC-28 LEAD FREE, PLASTIC, LCC-28 PLASTIC, LCC-28 5 X 5 MM, QFN-32 PLASTIC, LCC-28 5 X 5 MM, LEAD FREE, QFN-32 5 X 5 MM, QFN-32 - LEAD FREE, PLASTIC, LCC-28
针数 32 28 28 28 32 28 32 32 - 28
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 - EAR99 EAR99
架构 PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE - PAL-TYPE
最大时钟频率 303 MHz 91 MHz 50 MHz 167 MHz 143 MHz 50 MHz 143 MHz 100 MHz - 143 MHz
JESD-30 代码 S-XQCC-N32 S-PQCC-J28 S-PQCC-J28 S-PQCC-J28 S-XQCC-N32 S-PQCC-J28 S-XQCC-N32 S-XQCC-N32 - S-PQCC-J28
长度 5 mm 11.5062 mm 11.5062 mm 11.5062 mm 5 mm 11.5062 mm 5 mm 5 mm - 11.5062 mm
湿度敏感等级 1 1 1 1 1 1 1 1 - 1
专用输入次数 11 11 11 11 11 11 11 11 - 11
I/O 线路数量 10 10 10 10 10 10 10 10 - 10
输入次数 22 22 22 22 22 22 22 22 - 22
输出次数 10 10 10 10 10 10 10 10 - 10
产品条款数 132 132 132 132 132 132 132 132 - 132
组织 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O - 11 DEDICATED INPUTS, 10 I/O
输出函数 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL - MACROCELL
封装主体材料 UNSPECIFIED PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY UNSPECIFIED PLASTIC/EPOXY UNSPECIFIED UNSPECIFIED - PLASTIC/EPOXY
封装代码 HVQCCN QCCJ QCCJ QCCJ HVQCCN QCCJ HVQCCN HVQCCN - QCCJ
封装等效代码 LCC32,.2SQ,20 LDCC28,.5SQ LDCC28,.5SQ LDCC28,.5SQ LCC32,.2SQ,20 LDCC28,.5SQ LCC32,.2SQ,20 LCC32,.2SQ,20 - LDCC28,.5SQ
电源 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 2.5 V - 3.3 V
可编程逻辑类型 EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD - EE PLD
传播延迟 2.3 ns 7.5 ns 15 ns 4 ns 5 ns 15 ns 5 ns 7.5 ns - 5 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified - Not Qualified
座面最大高度 1 mm 4.572 mm 4.572 mm 4.572 mm 1 mm 4.572 mm 1 mm 1 mm - 4.572 mm
最大供电电压 3.6 V 3.6 V 3.6 V 3.6 V 2.7 V 3.6 V 3.6 V 2.7 V - 3.6 V
最小供电电压 3 V 3 V 3 V 3 V 2.3 V 3 V 3 V 2.3 V - 3 V
标称供电电压 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 2.5 V - 3.3 V
表面贴装 YES YES YES YES YES YES YES YES - YES
端子形式 NO LEAD J BEND J BEND J BEND NO LEAD J BEND NO LEAD NO LEAD - J BEND
端子节距 0.5 mm 1.27 mm 1.27 mm 1.27 mm 0.5 mm 1.27 mm 0.5 mm 0.5 mm - 1.27 mm
端子位置 QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD - QUAD
宽度 5 mm 11.5062 mm 11.5062 mm 11.5062 mm 5 mm 11.5062 mm 5 mm 5 mm - 11.5062 mm
Base Number Matches 1 1 1 1 1 1 - - - 1
JESD-609代码 - e0 e3 e0 - e0 e3 - - e3
最高工作温度 - 75 °C 75 °C 75 °C - 75 °C - - 160 °C 75 °C
端子面层 - Tin/Lead (Sn85Pb15) Matte Tin (Sn) Tin/Lead (Sn85Pb15) - Tin/Lead (Sn85Pb15) Matte Tin (Sn) - - Matte Tin (Sn)
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器件捷径:
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ
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