RNA52A10MM
Dual CMOS system–RESET IC
REJ03D0858-0500
Rev.5.00
Oct 06, 2008
Description
The RNA52A10MM incorporates two reset circuits, one with and one without a delay function, allowing the generation
of separate reset signals for a microprocessor and associated system circuits. The detection voltage of each reset circuit is
determined by the value of an external resistor, and the internal reference voltage is 1.0 V. The CMOS process for the
RNA52A10MM means that the device draws only 1.1
µA
(typ.). The reset cancellation delay time is set with a high
degree of accuracy by the values of a capacitor and resistor connected with the CD pin. The MR (manual reset) input pin
is provided for the reset circuit with the delay function, and the reset signal is output in response to a high level on the MR
input pin. The MR pin is pulled down by a 2-MΩ internal resistor. Output pins Vo1 and Vo2 are open drain.
Features
•
•
•
•
•
•
•
•
•
•
•
Two CMOS reset circuits, one with and one without the delay function
Reference voltage: 1.0 V
Reference voltage accuracy: ± 50 mV
Reference voltage hysteresis: 6% (typ.)
Low current consumption: 1.1
µA
(typ.)
Delay time set by an external CR circuit
Manual reset input
Open-drain output
MMPAK-8 (8-pin) package
Operating temperature range: – 40 to 85°C
Ordering Information
Part Name
RNA52A10MMEL
Package Type
MMPAK-8 pin
Package Code
PLSP0008JC-A
Package
Abbreviation
MM
Taping Abbreviation
(Quantity)
EL (3,000 pcs / Reel)
Application
•
•
•
•
•
•
•
Power-supply monitoring and resetting for microprocessors
Power supply sequence control for microprocessors
Desktop and laptop PCs
PC peripheral devices such as printers
Digital still cameras, digital video cameras, and PDAs
Battery-driven products
Wireless communications systems
REJ03D0858-0500 Rev.5.00 Oct 06, 2008
Page 1 of 11
RNA52A10MM
Pin Arrangement
MR
Vo1
Vo2
GND
1
2
3
4
8
7
6
5
VDD
Vi1
Vi2
CD
Outline and Article Indication
• RNA52A10MM
Index band
Marking
R 0 1
YMW
MMPAK–8
Lot No.
Y : Year code
(the last digit of year)
M : Month code
W : Week code
REJ03D0858-0500 Rev.5.00 Oct 06, 2008
Page 2 of 11
RNA52A10MM
Functional Block Diagram and Typical application Circuit
V
DD3
V
DD1
R
S1
Vi1
Reset circuit 1
R
L1
Vo1
2
V
DD4
7
R
S2
V
DD2
Reset circuit 2
R
L2
Vo2
R
S3
3
RESET
Vi2
6
R
S4
Micro-
computer
V
REF
1.0V
2M
8
VDD
1
MR
5
CD
GND
4
R
D
V
DD0
C
D
C
1
Notes: 1. Please refer to the following equations to set up reset-threshold voltages for power supplies V
DD1
and V
DD2
, and
to set up external voltage-dividing resistor pairs R
S1
and R
S2
, and R
S3
and R
S4
.
(1) V
DD1
reset-threshold voltage = V
REF
×
(R
S1
+R
S2
)/R
S2
(2) V
DD2
reset-threshold voltage = V
REF
×
(R
S3
+R
S4
)/R
S4
Note that values must be set up within the following range: R
S1
, R
S2
, R
S3
, R
S4
≤
50 kΩ
See the following graph for the relationship between the reference voltage variation and the value selected for
R
S1
, R
S2
, R
S3
and R
S4
.
2. For capacitor C1, select a type which has excellent frequency characteristics. For stable operation, place it
between the VDD pin and the GND pin and as close as is possible to the chip.
3. The value of capacitor C
1
must suit the system environment in terms of the quality of the power supply and so
forth.
Reference Voltage Variation vs. Parallel Resistance
Reference Voltage Variation [%]
5
4
3
2
1
0
-1
0.1
1
10
100
1000
Parallel Resistance (RS1//RS2, RS3//RS4) [kΩ]
REJ03D0858-0500 Rev.5.00 Oct 06, 2008
Page 3 of 11
RNA52A10MM
Timing Diagram
1. I/O Table
MR
L
H
Vi1, Vi2
≤
V
REF
≥
(V
REF
+V
HYS
)
≤
V
REF
≥
(V
REF
+V
HYS
)
Vo1
L
H
L
H
Vo2
L
H (after T
DLY0
)
L
2. Timing Chart
(V
REF
+V
HYS
)
V
REF
(V
REF
+V
HYS
)
Vi1, Vi2
V
DD0
MR
V
DD3
Vo1
T
DLY0
T
DLY0
T
DLY0
V
DD4
Vo2
Absolute Maximum Ratings
Item
Supply voltage (VDD)
Input voltage (Vi1, Vi2, MR, CD)
Output voltage (Vo1,
Vo2)
Output current (Vo1,
Vo2)
Continuous power dissipation
(Ta = 25°C, in still air)
Operating temperature
Storage temperature
Note:
Symbol
V
DD
V
IN
V
OUT
I
OUT
P
D
T
OPR
T
STG
Ratings
6.0
–0.3 to V
DD
–0.3 to 6.0
30
145
–40 to 85
–55 to 125
Unit
V
V
V
mA
mW
°C
°C
Refer to the relevant characteristic curve on page 6 for continuous power dissipation.
Recommended Operating Conditions
Item
Supply voltage (VDD)
Input voltage (Vi1, Vi2, MR, CD)
Output voltage (Vo1,
Vo2)
Output current (Vo1,
Vo2)
Operating temperature
Symbol
V
DD
V
IN
V
OUT
I
OUT
T
OPR
Min.
1.4
0
0
0
–40
Max.
5.5
V
DD
5.5
15
85
Unit
V
V
V
mA
°C
REJ03D0858-0500 Rev.5.00 Oct 06, 2008
Page 4 of 11
RNA52A10MM
Electrical Characteristics
(Ta = 25°C, unless otherwise noted)
Item
Supply voltage
Current consumption
Reference voltage
Reference voltage temperature
coefficient
(Reference value for design)
Vi1, Vi2 input
hysteresis voltage
Vi1, Vi2 input current
CD input threshold voltage
Symbol
V
DD
I
DD
V
REF
∆V
REF
V
REF
⋅∆T
a
Min.
1.4
—
0.95
—
28.5
(V
REF
×3%)
—
V
DD
×0.43
Typ.
—
1.1
1.00
±100
60
(V
REF
×6%)
0.6
V
DD
×0.63
Max.
5.5
19
1.05
—
94.5
(V
REF
×9%)
2.2
V
DD
×0.83
Unit
V
µA
V
ppm
°C
T
a
= –40 to 85°C
2
V
DD
= 5.5 V
V
i1
= V
i2
= 5.5 V
V
DD
= 3.3 V
Test Conditions
Test
Circuit
—
1
2
V
HYS
I
IN
V
DLY
mV
µA
V
V
DD
= 3.3 V
V
DD
= 5.5 V
V
i1
= V
i2
= 5.5 V
V
DD
= 3.3 V
V
i1
= V
i2
= 1.2 V
V
DD
= 1.4V
V
i1
= V
i2
= 0 V
I
OL
= 0.5 mA
V
DD
= 3.3V
2
3
4
—
Vo1, Vo2
low-level output voltage
V
OL
—
Vo1, Vo2
output leakage current
Incomplete
discharge of
capacity CD
complete
discharge of
capacity CD
0.05
0.15
V
5
0.15
0.35
V
V
i1
= V
i2
= 0 V
I
OL
= 5 mA
V
DD
= V
O1
= V
O2
= 5.5 V
V
i1
= V
i2
= 1.2 V
6
I
LK
—
—
100
nA
7
T
DLY
1.1
11
17
ms
Vo2
Note1
Delay time
V
DD
= 3.3 V
V
i2
= 0 V→1.2 V
C
D
= 0.3
µF,
R
D
= 39 kΩ
8
T
DLY0
7
11
17
ms
µs
8
Vo1
Rise response time
Vo1, Vo2
fall response time
MR low-level input voltage
V
DD
< 4.5V
T
PLH
—
30
300
V
DD
= 3.3 V
V
i1
= 0 V→1.2 V
V
DD
= 3.3 V
V
i1
= V
i2
= 1.2 V→0 V
C
D
= 0.3
µF,
R
D
= 39 kΩ
V
DD
= 3.3 V
V
i1
= V
i2
= 1.2 V
V
DD
= 3.3 V
V
i1
= V
i2
= 1.2 V
V
DD
= 5.0 V
V
i1
= V
i2
= 1.2 V
V
DD
= 5.5 V
V
MR
= 5.5 V
9
T
PHL
—
30
800
µs
10
V
IL
—
V
DD
×0.75
—
—
—
2
V
DD
×0.2
—
—
—
V
V
V
MΩ
11
11
12
13
MR high-level
input voltage
V
IH
V
DD
≥
4.5V
R
MR
V
DD
×0.5
0.5
MR input
pull-down resistance
Notes: 1. When capacitor C
D
is completely discharged and charging starts in the state that C
D
pin voltage is 0 V, the
minimum value of delay time T
DLY0
is 7 ms. However, when the discharging time is short and charging starts in
the state that the voltage does not completely fall to 0 V, the minimum value of delay time T
DLY
is 1.1 ms. Then,
the minimum value of Low time (reset time) of
Vo2
is 1.1 ms as the delay time T
DLY
. Refer to Regulations for
state of capacitor C
D
electrical discharge and delay time on page 10 for details.
2. Refer to the characteristic curves on page 6 for temperature dependence of the main characteristics.
3. Refer to pages 8 and 9 for the test circuits.
REJ03D0858-0500 Rev.5.00 Oct 06, 2008
Page 5 of 11
