Obsolete Device
Please use 24LC32A.
24C32A
32K 5.0V I
2
C
™
Serial EEPROM
FEATURES
• Voltage operating range: 4.5V to 5.5V
- Maximum write current 3 mA at 5.5V
- Standby current 1
µA
typical at 5.0V
• 2-wire serial interface bus, I
2
C compatible
• 100 kHz and 400 kHz compatibility
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Hardware write protect
• 1,000,000 Erase/Write cycles guaranteed
• 32-byte page or byte write modes available
• Schmitt trigger filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the
same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges
- Commercial (C):
0°C to
70°C
- Industrial (I):
-40°C to +85°C
- Automotive (E):
-40°C to +125°C
PACKAGE TYPES
PDIP
A0
A1
A2
Vss
1
24C32A
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
SOIC
A0
A1
A2
Vss
1
24C32A
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
DESCRIPTION
The Microchip Technology Inc. 24C32A is a 4K x 8
(32K bit) Serial Electrically Erasable PROM. It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
The 24C32A also has a page-write capability of up to
32 bytes of data. The 24C32A is capable of both ran-
dom and sequential reads up to the 32K boundary.
Functional address lines allow up to eight 24C32A
devices on the same bus, for up to 256K bits address
space. Advanced CMOS technology and broad voltage
range make this device ideal for low-power/low-volt-
age, nonvolatile code and data applications. The
24C32A is available in the standard 8-pin plastic DIP
and both 150 mil and 200 mil SOIC packaging.
BLOCK DIAGRAM
A0 A1 A2 WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
I/O
SCL
YDEC
SDA
V
CC
V
SS
SENSE AMP
R/W CONTROL
I
2
C is a trademark of Philips Corporation.
2004 Microchip Technology Inc.
DS21163E-page 1
24C32A
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
A0,A1,A2
V
SS
SDA
SCL
WP
V
CC
PIN FUNCTION TABLE
Function
User Configurable Chip Selects
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+4.5V to 5.5V Power Supply
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins
..................................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Vcc = +4.5V to 5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
Automotive(E): Tamb = -40°C to +125°C
Parameter
Symbol
A0, A1, A2, SCL , SDA and WP
pins:
High level input voltage
V
IH
Low level input voltage
V
IL
Hysteresis of Schmitt Trigger
V
HYS
inputs
Low level output voltage
V
OL
Input leakage current
I
LI
Output leakage current
I
LO
Pin capacitance
C
IN
, C
OUT
(all inputs/outputs)
Operating current
I
CC
Write
I
CC
Read
Standby current
I
CCS
Note:
Min
Typ
Max
Units
Conditions
.7 V
CC
—
.05
V
CC
—
-10
-10
—
—
—
—
—
.3 Vcc
—
.40
10
10
10
3
0.5
5
V
V
V
V
µA
µA
pF
mA
mA
µA
(Note)
I
OL
= 3.0 mA
V
IN
= .1V to V
CC
V
OUT
= .1V to V
CC
V
CC
= 5.0V (Note)
Tamb = 25°C, F
c
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V, SCL = 400 kHz
SCL = SDA = V
CC
= 5.5V
WP = V
SS
, A0, A1, A2 = V
SS
1
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU
:
STA
SDA
T
HD
:
STA
T
SU
:
STO
START
STOP
DS21163E-page 2
2004 Microchip Technology Inc.
24C32A
TABLE 1-3:
AC CHARACTERISTICS
Vcc = 4.5-5.5
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Output fall time from V
IH
min to
V
IL
max
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
Symbol
Min
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
T
OF
T
SP
T
WR
—
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
—
—
—
1M
Max
100
—
—
1000
300
—
—
—
—
—
3500
—
250
50
5
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
cycles
25°C, Vcc = 5.0V, Block Mode
(Note 4)
(Note 2)
Time the bus must be free before
a new transmission can start
(Note 1), C
B
≤
100 pF
(Note 3)
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
Units
Remarks
Note 1: Not 100% tested. C
B
= Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
SDA
IN
T
HD
:
STA
T
SP
T
AA
SDA
OUT
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
2004 Microchip Technology Inc.
DS21163E-page 3
24C32A
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24C32A supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the Serial Clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C32A works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
Note:
The 24C32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24C32A) will leave the data line HIGH to
enable the master to generate the STOP condition.
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1:
(A)
SCL
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
STOP
CONDITION
DS21163E-page 4
2004 Microchip Technology Inc.
24C32A
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code; for the 24C32A this is
set as 1010 binary for read and write (R/W) operations.
The next three bits of the control byte are the device
select bits (A2, A1, A0). They are used by the master
device to select which of the eight devices are to be
accessed. These bits are in effect the three most signif-
icant bits of the word address. The last bit of the control
byte defines the operation to be performed. When set
to a one a read operation is selected, and when set to
a zero a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 3-3). Because only A11...A0 are used, the
upper four address bits must be zeros. The most signif-
icant bit of the most significant byte of the address is
transferred first.
Following the start condition, the 24C32A monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24C32A will select a read or
write operation.
Operation
Read
Write
Control
Code
1010
1010
Device Select
Device Address
Device Address
R/W
1
0
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
READ/WRITE
START
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
A
2
A
1
A
0 R/W
ADDRESS BYTE 1
A
11
A
10
A
9
A
8
A
7
ADDRESS BYTE 0
•
•
•
•
•
•
A
0
1
0
1
0
0
0
0
0
SLAVE
ADDRESS
DEVICE
SELECT
BUS
2004 Microchip Technology Inc.
DS21163E-page 5
