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2SJ517

Silicon P Channel MOS FET

器件类别:分立半导体    晶体管   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

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器件参数
参数名称
属性值
包装说明
UPAK-3
针数
3
Reach Compliance Code
compli
ECCN代码
EAR99
外壳连接
DRAIN
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
20 V
最大漏极电流 (Abs) (ID)
2 A
最大漏极电流 (ID)
2 A
最大漏源导通电阻
0.43 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JESD-30 代码
R-PSSO-F3
元件数量
1
端子数量
3
工作模式
ENHANCEMENT MODE
最高工作温度
150 °C
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
极性/信道类型
P-CHANNEL
最大功率耗散 (Abs)
1 W
认证状态
Not Qualified
表面贴装
YES
端子形式
FLAT
端子位置
SINGLE
晶体管应用
SWITCHING
晶体管元件材料
SILICON
Base Number Matches
1
文档预览
2SJ517
Silicon P Channel MOS FET
REJ03G0874-0400
(Previous: ADE-208-575B)
Rev.4.00
Sep 07, 2005
Description
High speed power switching
Features
Low on-resistance
R
DS (on)
= 0.18
typ. (at V
GS
= –4 V, I
D
= –1 A)
Low drive current
High speed switching
2.5 V gate drive devices.
Outline
RENESAS Package code: PLZZ0004CA-A
(Package name: UPAK
R
)
D
3
2
1
G
4
1. Gate
2. Drain
3. Source
4. Drain
S
Note: Marking is “YY”.
*UPAK is a trademark of Renesas Technology Corp.
Rev.4.00 Sep 07, 2005 page 1 of 6
2SJ517
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body to drain diode reverse drain current
Channel dissipation
Channel temperature
Symbol
V
DSS
V
GSS
I
D
I
D (pulse)
I
DR
Note 1
Value
–20
±10
–2
–4
–2
1
150
–55 to +150
Unit
V
V
A
A
A
W
°C
°C
Pch
Tch
Note 2
Storage temperature
Tstg
Notes: 1. PW
100
µs,
duty cycle
10%
2. When using the aluminium ceramic board (12.5
×
20
×
0.7 mm)
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate to source breakdown voltage
Zero gate voltage drain current
Gate to source leak current
Gate to source cutoff voltage
Static drain to source on state resistance
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Body to drain diode forward voltage
Body to drain diode reverse recovery
time
Note:
3. Pulse test
Symbol
V
(BR) DSS
V
(BR) GSS
I
DSS
I
GSS
V
GS (off)
R
DS (on)
R
DS (on)
|y
fs
|
Ciss
Coss
Crss
t
d (on)
t
r
t
d (off)
t
f
V
DF
t
rr
Min
–20
±10
–0.5
1.8
Typ
0.18
0.27
3.0
320
190
90
14
75
90
90
–0.95
70
Max
–10
±10
–1.5
0.24
0.43
Unit
V
V
µA
µA
V
S
pF
pF
pF
ns
ns
ns
ns
V
ns
Test Conditions
I
D
= –10 mA, V
GS
= 0
I
G
=
±100 µA,
V
DS
= 0
V
DS
= –20 V, V
GS
= 0
V
GS
=
±8
V, V
DS
= 0
I
D
= –1 mA, V
DS
= –10 V
I
D
= –1 A, V
GS
= –4 V
Note 3
I
D
= –1 A, V
GS
= –2.5 V
I
D
= –1 A, V
DS
= –10 V
V
DS
= –10 V
V
GS
= 0
f = 1 MHz
V
GS
= –4 V
I
D
= –1 A
R
L
= 10
I
F
= –2 A, V
GS
= 0
I
F
= –2 A, V
GS
= 0
di
F
/dt = 50 A/µs
Note 3
Note 3
Rev.4.00 Sep 07, 2005 page 2 of 6
2SJ517
Main Characteristics
Power vs. Temperature Derating
2.0
Maximum Safe Operation Area
–10
10
Pch (W)
I
D
(A)
Test Condition:
When using the aluminum ceramic
board (12.5
×
20
×
70 mm)
–3
–1
1.5
PW
µ
s
10
=
10
1
m
s
m
0
s
µ
s
Channel Dissipation
Drain Current
D
C
–0.3
1.0
O
(1
pe
sh
ra
ot
)
0.5
–0.1 Operation in
this area is
limited by R
DS (on)
–0.03
Ta = 25°C
–0.01
–1
–0.1 –0.3
tio
n
0
0
50
100
150
200
–3
–10
–30
–100
Ambient Temperature
Ta (°C)
Drain to Source Voltage V
DS
(V)
Typical Output Characteristics
–5
–10 V
–5
Pulse Test
–2.5 V
–4 V
–3 V
Typical Transfer Characteristics
V
DS
= –10 V
Pulse Test
I
D
(A)
I
D
(A)
–4
–4
–25°C
–3
25°C
Tc = 75°C
–3
Drain Current
–2
–2 V
Drain Current
–10
–2
–1
V
GS
= –1.5 V
0
0
–2
–4
–6
–8
–1
0
0
–1
–2
–3
–4
–5
Drain to Source Voltage
V
DS
(V)
Gate to Source Voltage
V
GS
(V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Drain to Source on State Resistance
R
DS (on)
(Ω)
Drain to Source Saturation Voltage
V
DS (on)
(V)
–1.0
Pulse Test
Static Drain to Source on State Resistance
vs. Drain Current
1
0.5
V
GS
= –2.5 V
0.2
0.1
0.05
–4 V
–0.8
–0.6
–0.4
I
D
= –2 A
–0.2
–1 A
–0.5 A
0
0
–2
–4
–6
–8
–10
0.02
Pulse Test
0.01
–0.1 –0.2 –0.5
–1
–2
–5
–10
Gate to Source Voltage
V
GS
(V)
Drain Current
I
D
(A)
Rev.4.00 Sep 07, 2005 page 3 of 6
2SJ517
Static Drain to Source on State Resistance
vs. Temperature
Forward Transfer Admittance vs.
Drain Current
Forward Transfer Admittance |yfs| (S)
Static Drain to Source on State Resistance
R
DS (on)
(Ω)
0.5
Pulse Test
0.4
V
GS
= –2.5 V
0.3
–1 A
–0.5 A
I
D
= –2 A
10
5
Tc = –25°C
25°C
2
1
75°C
0.5
0.2
–0.5 A, –1 A, –2 A
0.1
–4 V
0.2
0.1
–0.1
V
DS
= –10 V
Pulse Test
–0.2
–0.5
–1
–2
–5
–10
0
–40
0
40
80
120
160
Case Temperature
Tc (°C)
Drain Current I
D
(A)
Typical Capacitance vs.
Drain to Source Voltage
1000
500
Body-Drain Diode Reverse
Recovery Time
500
Reverse Recovery Time trr (ns)
Capacitance C (pF)
200
100
50
Ciss
200
100
50
Coss
Crss
20
10
5
–0.1 –0.2
di / dt = 50 A /
µs
V
GS
= 0, Ta = 25°C
–0.5
–1
–2
–5
–20
20
10
V
GS
= 0
f = 1 MHz
0
–4
–8
–12
–16
–20
Reverse Drain Current
I
DR
(A)
Drain to Source Voltage V
DS
(V)
Dynamic Input Characteristics
Switching Characteristics
V
DS
(V)
V
DD
= –5 V
–10 V
–10
V
DS
–20
V
DD
= –5 V
–10 V
V
GS
–40
–16
–8
–4
V
GS
(V)
0
0
500
Switching Time t (ns)
200
td(off)
100
50
tf
tr
Drain to Source Voltage
–30
–12
Gate to Source Voltage
20
10
5
–0.1 –0.2
td(on)
V
GS
= –4 V, V
DD
= –10 V
duty
1 %
–0.5
–1
–2
–5
–10
–50
0
4
8
12
16
–20
20
Gate Charge
Qg (nc)
Drain Current
I
D
(A)
Rev.4.00 Sep 07, 2005 page 4 of 6
2SJ517
Reverse Drain Current vs.
Source to Drain Voltage
–5
Reverse Drain Current I
DR
(A)
–4
–4 V
–3
–2
–2.5 V
–1
V
GS
= 0, 5 V
Pulse Test
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
Source to Drain Voltage
V
SD
(V)
Switching Time Test Circuit
Vin
Vin Monitor
D.U.T.
R
L
Vout
Monitor
10%
Waveform
90%
90%
90%
Vin
4V
50
V
DD
= –10 V
Vout
td(on)
10%
tr
td(off)
10%
tf
Rev.4.00 Sep 07, 2005 page 5 of 6
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参数对比
与2SJ517相近的元器件有:2SJ517YYTL-E、2SJ517YYTR-E。描述及对比如下:
型号 2SJ517 2SJ517YYTL-E 2SJ517YYTR-E
描述 Silicon P Channel MOS FET Silicon P Channel MOS FET Silicon P Channel MOS FET
包装说明 UPAK-3 SMALL OUTLINE, R-PSSO-F3 SMALL OUTLINE, R-PSSO-F3
针数 3 4 4
Reach Compliance Code compli compli unknow
ECCN代码 EAR99 EAR99 EAR99
外壳连接 DRAIN DRAIN DRAIN
配置 SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压 20 V 20 V 20 V
最大漏极电流 (Abs) (ID) 2 A 2 A 2 A
最大漏极电流 (ID) 2 A 2 A 2 A
最大漏源导通电阻 0.43 Ω 0.43 Ω 0.43 Ω
FET 技术 METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 代码 R-PSSO-F3 R-PSSO-F3 R-PSSO-F3
元件数量 1 1 1
端子数量 3 3 3
工作模式 ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
最高工作温度 150 °C 150 °C 150 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
极性/信道类型 P-CHANNEL P-CHANNEL P-CHANNEL
最大功率耗散 (Abs) 1 W 1 W 1 W
认证状态 Not Qualified Not Qualified Not Qualified
表面贴装 YES YES YES
端子形式 FLAT FLAT FLAT
端子位置 SINGLE SINGLE SINGLE
晶体管应用 SWITCHING SWITCHING SWITCHING
晶体管元件材料 SILICON SILICON SILICON
Base Number Matches 1 1 1
Brand Name - Renesas Renesas
是否Rohs认证 - 符合 符合
零件包装代码 - UPAK UPAK
制造商包装代码 - PLZZ0004CA-A4 PLZZ0004CA-A4
湿度敏感等级 - 1 1
峰值回流温度(摄氏度) - 260 260
处于峰值回流温度下的最长时间 - NOT SPECIFIED NOT SPECIFIED
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