CD4069UBC Inverter Circuits
October 1987
Revised January 1999
CD4069UBC
Inverter Circuits
General Description
The CD4069UB consists of six inverter circuits and is man-
ufactured using complementary MOS (CMOS) to achieve
wide power supply operating range, low power consump-
tion, high noise immunity, and symmetric controlled rise
and fall times.
This device is intended for all general purpose inverter
applications where the special characteristics of the
MM74C901, MM74C907, and CD4049A Hex Inverter/Buff-
ers are not required. In those applications requiring larger
noise immunity the MM74C14 or MM74C914 Hex Schmitt
Trigger is suggested.
All inputs are protected from damage due to static dis-
charge by diode clamps to V
DD
and V
SS
.
Features
s
Wide supply voltage range:
s
High noise immunity:
3.0V to 15V
0.45 V
DD
typ.
s
Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s
Equivalent to MM74C04
Ordering Code:
Order Number
CD4069UBCM
CD4069UBCSJ
CD4069UBCN
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram
Pin Assignments for SOIC and DIP
Schematic Diagram
© 1999 Fairchild Semiconductor Corporation
DS005975.prf
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CD4069UBC
Absolute Maximum Ratings
(Note 1)
(Note 2)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260°C
700 mW
500 mW
−0.5V
to
+18
V
DC
−0.5V
to V
DD
+0.5
V
DC
−65°C
to
+150°C
Recommended Operating
Conditions
(Note 2)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
3V to 15V
DC
0V to V
DD
V
DC
−40°C
to
+85°C
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of “Recom-
mended Operating Conditions” and Electrical Characteristics table provide
conditions for actual device operation.
Note 2:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 3)
Symbol
I
DD
Parameter
Quiescent Device Current
V
DD
=
5V,
V
IN
=
V
DD
or V
SS
V
DD
=
10V,
V
IN
=
V
DD
or V
SS
V
DD
=
15V,
V
IN
=
V
DD
or V
SS
V
OL
LOW Level Output Voltage
|I
O
|
<
1
µA
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
OH
HIGH Level Output Voltage
|I
O
|
<
1
µA
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
IL
LOW Level Input Voltage
|I
O
|
<
1
µA
V
DD
=
5V, V
O
=
4.5V
V
DD
=
10V, V
O
=
9V
V
DD
=
15V, V
O
=
13.5V
V
IH
HIGH Level Input Voltage
|I
O
|
<
1
µA
V
DD
=
5V, V
O
=
0.5V
V
DD
=
10V, V
O
=
1V
V
DD
=
15V, V
O
=
1.5V
I
OL
LOW Level Output Current
(Note 4)
I
OH
HIGH Level Output Current
(Note 4)
I
IN
Input Current
V
DD
=
5V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
4.6V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
Note 3:
V
SS
=
0V unless otherwise specified.
Note 4:
I
OH
and I
OL
are tested one output at a time.
Conditions
−40°C
Min
Max
1.0
2.0
4.0
Min
+25°C
Typ
Max
1.0
2.0
4.0
+85°C
Min
Max
7.5
15
30
Units
µA
µA
µA
0.05
0.05
0.05
4.95
9.95
14.95
1.0
2.0
3.0
4.0
8.0
12.0
0.52
1.3
3.6
−0.52
−1.3
−3.6
−0.30
0.30
4.0
8.0
12.0
0.44
1.1
3.0
−0.44
−1.1
−3.0
4.95
9.95
14.95
0
0
0
0.05
0.05
0.05
4.95
9.95
14.95
1.0
2.0
3.0
4.0
8.0
12.0
0.05
0.05
0.05
V
V
V
V
V
V
1.0
2.0
3.0
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
0.88
2.25
8.8
−0.88
−2.25
−8.8
−10
−5
10
−5
−0.30
0.30
0.36
0.9
2.4
−0.36
−0.9
−2.4
−1.0
1.0
µA
µA
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2
CD4069UBC
AC Electrical Characteristics
Symbol
t
PHL
or t
PLH
Parameter
Propagation Delay Time from
Input to Output
t
THL
or t
TLH
Transition Time
(Note 5)
Conditions
Min
Typ
50
30
25
80
50
40
6
12
Max
90
60
50
150
100
80
15
Units
ns
ns
ns
ns
ns
ns
pF
pF
T
A
=
25°C, C
L
=
50 pF, R
L
=
200 kΩ, t
r
and t
f
≤
20 ns, unless otherwise specified
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
C
IN
C
PD
Average Input Capacitance
Power Dissipation Capacitance
Any Gate
Any Gate (Note 6)
Note 5:
AC Parameters are guaranteed by DC correlated testing.
Note 6:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note—
AN-90.
AC Test Circuits and Switching Time Waveforms
3
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CD4069UBC
Typical Performance Characteristics
Gate Transfer Characteristics
Ambient Temperature
Power Dissipation vs
Frequency
Propagation Delay vs
Ambient Temperature
Propagation Delay vs
Propagation Delay Time
vs Load Capacitance
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4
CD4069UBC
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm wide
Package Number M14D
5
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