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5962G9652601QCX

NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDIP14, CERAMIC, SIDE BRAZED, DIP-14

器件类别:逻辑    逻辑   

厂商名称:Cobham PLC

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器件参数
参数名称
属性值
厂商名称
Cobham PLC
包装说明
DIP,
Reach Compliance Code
unknown
系列
AC
JESD-30 代码
R-CDIP-T14
逻辑集成电路类型
NAND GATE
功能数量
2
输入次数
4
端子数量
14
最高工作温度
125 °C
最低工作温度
-55 °C
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
传播延迟(tpd)
15 ns
认证状态
Not Qualified
筛选级别
MIL-PRF-38535 Class Q
座面最大高度
5.08 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
总剂量
500k Rad(Si) V
宽度
7.62 mm
Base Number Matches
1
文档预览
Standard Products
UT54ACS20/UT54ACTS20
Dual 4-Input NAND Gates
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS20 - SMD 5962-96526
UT54ACTS20 - SMD 5962-96527
DESCRIPTION
The UT54ACS20 and the UT54ACTS20 are dual 4-input
NAND gates. The circuits perform the Boolean functions
Y = A⋅B⋅C⋅D or Y = A + B + C + D in positive logic.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
A
H
L
X
X
X
B
H
X
L
X
X
C
H
X
X
L
X
D
H
X
X
X
L
OUTPUT
Y
L
H
H
H
H
PINOUTS
14-Pin DIP
Top View
A1
B1
NC
C1
D1
Y1
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
D2
C2
NC
B2
A2
Y2
14-Lead Flatpack
Top View
A1
B1
NC
C1
D1
Y1
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
D2
C2
NC
B2
A2
Y2
LOGIC DIAGRAM
A1
B1
C1
D1
A2
B2
C2
D2
Y1
LOGIC SYMBOL
A1
B1
C1
D1
A2
B2
C2
D2
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(8)
Y2
(6)
Y1
&
Y2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
2
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
ΔI
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 8.0mA
I
OL
= 100μA
I
OH
= -8.0mA
I
OH
= -100μA
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
15
15
pF
pF
1.9
10
1.6
mW/
MHz
μA
mA
-8
mA
.7V
DD
V
DD
- 0.25
-200
8
200
.5V
DD
.7V
DD
-1
1
0.40
0.25
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
μA
V
V
OH
V
I
OS
I
OL
mA
mA
3
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
4
AC ELECTRICAL CHARACTERISTICS
2
(V
DD
= 5.0V
±10%;
V
SS
= 0V
1
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
t
PHL
t
PLH
Input to Yn
Input to Yn
PARAMETER
MINIMUM
1
1
MAXIMUM
15
11
UNIT
ns
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose
1E6 rads(Si).
5
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