DATASHEET
MPEG CLOCK SYNTHESIZER
Description
The ICS650-12 is a low cost, low-jitter, high-performance
clock synthesizer designed to produce fixed clock outputs of
13.5 MHz and 27.0 MHz, and four selectable clock outputs:
two Processor Clocks (PCLK1) and PCLK2), an Audio
Clock, and a Communications Clock (CCLK). Using analog
Phase-Locked Loop (PLL) techniques, the device uses a
27.0 MHz clock or fundamental crystal to produce clocks
ideal for Digital Video/MPEG-based applications.
ICS650-12
Features
•
Packaged in 20-pin tiny SSOP (QSOP)
•
Available in RoHS 5 (green) or RoHS 6 (green and lead
free) compliant package
•
Input frequency of 27.0 MHz
•
Zero ppm synthesis error in output clocks
•
Provides fixed 13.5 MHz and 27.0 MHz. Also provides
•
•
•
two selectable processor clocks, one audio clock, and
one communications clock.
Ideal for digital video MPEG-based applications
3.3 V or 5.0 V operating voltage
Entire chip powers down (when CS1=CS0=0)
Block Diagram
PS2:0
AS2:0
CS1:0
Clock
Synthesis
and Control
Circuitry
PCLK1
PCLK2
ACLK
CCLK
13.5 MHz
27.0 MHz crystal
or clock
Input
Buffer/
Crystal
Oscillator
/2
27.0 MHz
IDT™ / ICS™
MPEG CLOCK SYNTHESIZER
1
ICS650-12
REV C 051206
ICS650-12
MPEG CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Pin Assignment
PS2
X2
X1
VDD
CS1
GND
ACLK
PCLK1
CS0
AS2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PS1
PS0
CCLK
PCLK2
VDD
AS1
GND
13.5M
27M
AS0
ACLK Select Table (in MHz)
AS2
0
0
0
0
1
1
1
1
AS1
0
0
1
1
0
0
1
1
AS0
0
1
0
1
0
1
0
1
ACLK
12.288
11.2896
8.192
24.576
8.192
16.9344
18.432
11.2896
20-pin SSOP (QSOP)
CCLK Select Table (in MHz)
PCLK1 and PCLK2 Select Table (in MHz)
CS1
0
0
1
1
CS0
0
1
0
1
CCLK
All off*
20.00
66.6666
24.576
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
PCLK1
108.00
55.00
66.67
80.00
54.00
81.00
50.00
60.00
PCLK2
54.00
27.5
33.33
40.00
27.00
40.5
25.00
30.00
*Note: Entire chip powers-down (outputs stop low) when
CS1=CS0=0.
IDT™ / ICS™
MPEG CLOCK SYNTHESIZER
2
ICS650-12
REV C 051206
ICS650-12
MPEG CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Pin Descriptions
Pin
Pin
Pin
Number Name Type
1
2
3
4, 16
5
6, 14
7
8
9
10
11
12
13
15
17
18
19
20
PS2
X2
X1
VDD
CS1
GND
ACLK
PCLK1
CS0
AS2
AS0
27M
13.5M
AS1
PCLK2
CCLK
PS0
PS1
Input
XO
XI
Power
Input
Power
Output
Output
Input
Input
Input
Output
Output
Input
Output
Output
Input
Input
Pin Description
Processor Clock Select pin 2. See table on page 2.
Crystal connection. Connect to a 27.0 MHz crystal or leave unconnected for a clock input.
Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.
Connect to +3.3 V or +5 V.
Communications Clock Select Pin 1. See table on page 2.
Connect to ground.
Audio Clock Output. See table on page 2.
Processor Clock Output 1. See table on page 2.
Communications Clock Select 0. See table on page 2.
Audio Clock Select Pin 2. See table on page 2.
Audio Clock Select Pin 0. See table on page 2.
27 MHz buffered clock output.
13.5 MHz clock output.
Audio Clock Select Pin 1. See table on page 2.
Processor Clock Output 2. See table on page 2.
Communications Clock Output. See table on page 2.
Processor Clock Select Pin 0. See table on page 2.
Processor Clock Select Pin 1. See table on page 2.
Key:
Input
= input with internal pull-up;
XI
and
XO
= crystal
connections;
Power
= power supply connection;
Output
=
output
IDT™ / ICS™
MPEG CLOCK SYNTHESIZER
3
ICS650-12
REV C 051206
ICS650-12
MPEG CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-12. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
Conditions
Referenced to GND
Referenced to GND
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
Max. of 10 seconds
260° C
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V or 5 V,
Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Operating Supply Current
Operating Supply Current
Short Circuit Current
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
V
OH,
VDD = 3.3
or 5 V
I
DD
@5 V
I
DD
@5 V
VDD = 3.3 V, I
OH
= -8 mA
VDD = 3.3 V, I
OL
= 8 mA
I
OH
= -8 mA
No Load
No Load
Except X1
VDD-0.4
39
22
±50
7
2.4
0.8
Conditions
Min.
3.0
2
VDD/2
VDD/2
0.8
Typ.
Max.
5.5
Units
V
V
V
V
V
V
mA
mA
mA
pF
I
OS,
VDD = 3.3 V Each output
IDT™ / ICS™
MPEG CLOCK SYNTHESIZER
4
ICS650-12
REV C 051206
ICS650-12
MPEG CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V or 5 V,
Ambient Temperature 0 to +70° C
Parameter
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
One Sigma Jitter, ACLK
Absolute Clock Period Jitter
Symbol
Conditions
All clocks
Min.
Typ.
27
0
Max. Units
MHz
1
1.5
1.5
ppm
ns
ns
%
ps
ps
ps
ps
t
OR
t
OF
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
VDD = 3.3 V
VDD = 5.0 V
VDD = 3.3 V, except
CCLK = 20 MHz
VDD = 5.0 V, except
CCLK = 20 MHz
40
50
100
40
±300
±200
60
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF
should be connected between VDD and GND on pins 4 and 6, 16 and 14, and a 33Ω terminating resistor may be
used on each clock output if the trace is longer than 1 inch.
IDT™ / ICS™
MPEG CLOCK SYNTHESIZER
5
ICS650-12
REV C 051206
