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6AM11
Silicon N-Channel/P-Channel Power MOS FET Array
ADE-208-1215 (Z)
1st. Edition
Mar. 2001
Application
High speed power switching
Features
•
Low on-resistance
N-channel: R
DS(on)
≤
0.17 , V
GS
= 10 V, I
D
= 2.5 A
P-channel: R
DS(on)
≤
0.2 , V
GS
= –10 V, I
D
= –2.5 A
•
Capable of 4 V gate drive
•
Low drive current
•
High speed switching
•
High density mounting
•
Suitable for H-bridged motor driver
6AM11
Outline
SP-12
5
S
Pch
6
G
4G
11
G
12
S
12
Nch
2G
D3
8
G
D7
9
G
D 10
34
56
78
9 10
1112
S
1
N-ch Source
1.
2, 8, 9 N-ch Gate
3, 7, 10. N-ch Drain
P-ch Drain
4, 6, 11. P-ch Gate
5, 12. P-ch Source
Absolute Maximum Ratings
(Ta = 25°C) (1 Unit)
Ratings
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body to drain diode reverse drain current
Channel dissipation
Symbol
V
DSS
V
GSS
I
D
I
D(pulse)
*
1
I
DR
Pch*
2
Channel temperature
Storage temperature
Notes: 1. PW
≤
10 µs, duty cycle
≤
1%
2. 6 Device Operation
Tch
Tstg
Nch
60
±20
5
20
5
Pch
–60
±20
–5
–20
–5
Unit
V
V
A
A
A
W
W
°C
°C
Pch (Tc = 25°C)*
2
36
4.8
150
–55 to +150
6AM11
Electrical Characteristics
(Ta = 25°C) (1 Unit)
N channel
Item
Drain to source
breakdown voltage
Gate to source
breakdown voltage
Gate to source leak
current
Symbol
V
(BR)DSS
V
(BR)GSS
I
GSS
Min
60
±20
—
—
1.0
—
—
Forward transfer
admittance
Input capacitance
Output capacitance
Reverse transfer
capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Body to drain diode
forward voltage
Body to drain diode
reverse recovery time
Note:
|y
fs
|
Ciss
Coss
Crss
t
d(on)
t
r
t
d(off)
t
f
V
DF
t
rr
2.7
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
0.13
0.18
4.5
400
220
60
5
30
170
75
1.0
100
Max
—
—
±10
250
2.0
0.17
0.24
—
—
—
—
—
—
—
—
—
—
P channel
Min
–60
±20
—
—
–1.0
—
—
2.7
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
0.15
0.20
5.0
900
460
130
8
35
180
85
–1.0
170
Max
—
—
±10
Unit
V
V
µA
Test conditions
I
D
= 10 mA, V
GS
= 0
I
G
= ±100 µA, V
DS
= 0
V
GS
= ±16 V, V
DS
= 0
V
DS
= 50 V, V
GS
= 0
I
D
= 1 mA, V
DS
= 10 V
I
D
= 2.5 A,
V
GS
= 10 V*
1
I
D
= 2.5 A, V
GS
= 4 V*
1
I
D
= 2.5 A,
V
DS
= 10 V*
1
V
DS
= 10 V, V
GS
= 0,
f = 1 MHz
Zero gate voltage drain I
DSS
current
Gate to source cutoff
voltage
Static drain to source
on state resistance
V
GS(off)
R
DS(on)
–250 µA
–2.0
0.2
0.27
—
—
—
—
—
—
—
—
—
—
V
Ω
Ω
S
pF
pF
pF
ns
ns
ns
ns
V
ns
I
D
= 2.5 A, V
GS
= 10 V,
R
L
= 12
Ω
I
F
= 5 A, V
GS
= 0
I
F
= 5 A, V
GS
= 0,
diF/dt = 50 A/µs
1. Pulse Test
Polarity of test conditions for P channel device is reversed.
