HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
IDT7008S/L
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/55ns (max.)
– Military: 25/35/55ns (max.)
Low-power operation
– IDT7008S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7008L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-7L
I/O
Control
I/O
Control
I/O
0-7R
BUSY
L
A
15L
A
0L
(1,2)
BUSY
R
64Kx8
MEMORY
ARRAY
7008
16
16
(1,2)
Address
Decoder
Address
Decoder
A
15R
A
0R
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
3198 drw 01
M/S
(1)
NOTES:
1.
BUSY
is an input as a Slave (M/S = V
IL
) and an output when it is a Master (M/S = V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
OCTOBER 2014
DSC 3198/10
1
©2014 Integrated Device Technology, Inc.
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The
IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
Description
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE
0
and CE
1
) permit the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power.
The IDT7008 is packaged in a 84-pin Ceramic Pin Grid Array (PGA),
a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad
Flatpack (TQFP).
Pin Configurations
(1,2,3)
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
NC
GND
NC
NC
CE
0R
CE
1R
SEM
R
R/W
R
OE
R
GND
11 10 9
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
8 7
6 5
4 3
08/19/14
INDEX
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
GND
BUSY
L
INT
L
NC
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
2 1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
GND
NC
NC
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
Vcc
I/O
2R
I/O
1R
I/O
0R
GND
Vcc
I/O
0L
I/O1
L
GND
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
3198 drw 02
IDT7008J
ID70J
T08
J84
J84
(4)
(4)
84-Pin PLCC
Top View
(5)
55
31
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
NC
Vcc
NC
NC
CE
0L
CE
1L
SEM
L
RIW
L
OE
L
GND
NOTES:
1. This text does not indicate orientation of the actual part marking.
2. All Vcc pins must be connected to power supply.
3. Package body is approximately 1.15 in x 1.15 in x .17 in.
4. This package code is used to reference the package diagram.
5. All GND pins must be connected to ground supply.
2
GND
NC
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
NOTES:
1. This text does not indicate orientation of the actual part marking.
2. All Vcc pins must be connected to power supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. All GND pins must be connected to ground supply.
3
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't)
08/19/14
63
61
60
58
55
54
51
48
46
45
42
11
66
A
7R
64
A
9R
A
10R
62
A
12R
59
A
15R
56
NC
49
50
NC
SEM
R
47
OE
R
44
GND
43
40
NC
10
67
A
4R
65
A
6R
A
8R
A
11R
A
14R
CE
1R
57
53
CE
0R
R/W
R
52
GND
41
NC
I/O
6R
39
09
69
A
3R
68
A
5R
A
13R
GND
NC
I/O
7R
I/O
5R
38
37
08
72
A
1R
71
A
2R
73
33
I/O
4R
I/O
3R
35
34
07
BUSY
R
INT
R
75
70
M
/S
74
IDT7008G
G84
(4)
84-PIN PGA
TOP VIEW
(5)
I/O
0R
I/O
2R
32
31
I/O
1R
36
06
BUSY
L
76
A
0R
77
GND
78
GND
28
29
Vcc
Vcc
30
05
04
INT
L
79
80
NC
A
0L
GND
I/O1
L
26
I/O
0L
27
A
1L
81
83
A
2L
7
11
12
I/O
3L
23
I/O
2L
25
03
82
A
3L
1
A
5L
2
5
8
A
13L
10
Vcc
14
NC
17
20
I/O
6L
22
I/O
4L
24
02
84
A
4L
3
A
7L
4
A
8L
6
A
11L
9
A
14L
15
NC
CE
0L
13
R/W
L
16
GND
18
I/O
7L
19
I/O
5L
21
01
A
6L
A
A
9L
B
A
10L
C
A
12L
D
A
15L
E
CE
1L
F
NC
G
SEM
L
H
OE
L
J
GND
K
NC
L
3198 drw 04
INDEX
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
15L
I/O
0L
- I/O
7L
SEM
L
INT
L
BUSY
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
15R
I/O
0R
- I/O
7R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
3198 tbl 01
4
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Chip Enable
(1)
CE
L
CE
0
V
IL
< 0.2V
V
IH
X
H
>V
CC
-0.2V
X
CE
1
V
IH
>V
CC
-0.2V
X
V
IL
X
<0.2V
Port Selected (TTL Active)
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
3198 tbl 02
Mode
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels,
CE
is a reference only.
Truth Table II: Non-Contention Read/Write Control
Inputs
(1)
CE
(2)
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to memory
Read memory
Outputs Disabled
3198 tbl 03
Mode
NOTES:
1. A
0L
– A
15L
≠
A
0R
– A
15R.
2. Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control
(1)
Inputs
CE
(2)
H
H
L
R/W
H
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-7
DATA
OUT
DATA
IN
______
Mode
Read Semaphore Flag Data Out
Write I/O
0
into Semaphore Flag
Not Allowed
3198 tbl 04
↑
X
NOTES:
1. There are eight semaphore flags written to via I/O
0
and read from all the I/Os (I/O
0
-I/O
7
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
5
6.42
