73M1866B/73M1966B
MicroDAA™ with PCM Highway
Simplifying System Integration™
DS_1x66B_001
DESCRIPTION
The 73M1866B and 73M1966B use the Teridian
patented Data Access Arrangement function
®
(MicroDAA ) designed exclusively for Foreign-
Exchange-Office (FXO) in Voice-over-IP (VoIP)
applications. These devices provide much of the
circuitry required to connect PCM formatted
voice channels to a PSTN via a two-wire twisted
pair interface. The package options provide the
necessary functional programmability and
protection required for easy worldwide
homologation.
The family of devices consists of the 73M1866B
and the 73M1966B. The 73M1866B MicroDAA
is the world’s first single-package silicon Data
Access Arrangement (DAA). Suitable
applications for the 73M1866B and 73M1966B
devices include VoIP equipment that must
provide connectivity to the PSTN for purposes of
guaranteeing emergency service calling,
redundancy for supplementary connectivity for
voice, and maintenance services.
The 73M1966B device set consists of the
73M1906B Host-Side Device that provides digital
data, control interfaces and power to the
73M1916 Line-Side Device.
These devices are based on an innovative and
patented technology, which sets new standards
in reliability and cost. A small pulse transformer
forms a digital isolation barrier, transferring both
power and data to the PSTN line-side
components. This method results in reliable
operation in the presence of EMI and a tolerance
to line voltage variations by providing power to
the Line-Side Device across the barrier. The
devices also support the ability to provide up to
an additional +6 dB of analog gain to the line-
side transmit and +3 dB in the receive signal
paths. The device supports transmit and receive
digital gain ranging from –18 dB to +7.375 dB by
increments of 0.125 dB.
DATA SHEET
April 2010
Through its PCM interface, the 73M1966B can
be connected to other PCM enabled devices
such as POTS codecs, ISDN codecs, E1/T1
framers, etc.
Additional DAA functions supported by the
73M1x66B devices include a call progress
monitor, Caller ID Type I and II, ring detection,
pulse dialing, billing tone detection and polarity
reversal detection.
APPLICATIONS
•
•
•
•
•
•
Computer Telephony
VOIP Equipment
PBX Systems
Internet Appliances
Voicemail Systems
POTS Termination Equipment
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PCM highway data interface supporting both
slave and master modes
PCM highway interface supporting both E-1
and T-1
SPI control interface, with daisy chain
support for up to 16 devices
Designed to meet global DAA compliance
FCC, ETSI ES 203 021-2, JATE and other
PTT standards.
8 kHz and 16 kHz sample rates
16-bit linear mode
TX and RX gains adjustable in 0.125 dB
increments
μ-Law,
A-law
ITU-T Recommendation G.711
compliant compander operation
Automatic clock rate detection
Low power modes
Polarity Reversal detection
GPIO for user-configurable I/O ports
Call Progress Monitor
Isolation up to 6 kV
THD -80 dB
5 V tolerant I/O on selected pins
3.0 V – 3.6 V operating voltage
Industrial temperature range (-40
°C
to +85
°C)
5x5 mm 32-pin QFN or 20-pin TSSOP
packages
RoHS compliant (6/6) lead-free package
The digital side provides a PCM highway
interface with automatic clock rate detection.
With an 8-kHz sampling rate, the devices include
an ITU-T G.711 compliant codec with selectable
µ-law and A-law companding modes. The
devices also provide a 16-bit linear mode, which
•
is suitable for interfacing with wide band codecs,
as well as 16 kHz sampling rate. Device control
is performed over an SPI interface. The SPI
supports daisy chain operation.
Rev. 1.6
© 2010 Teridian Semiconductor Corporation
1
73M1866B/73M1966B Data Sheet
DS_1x66B_001
Table of Contents
1
2
Introduction ................................................................................................................................... 6
Pinout ............................................................................................................................................. 8
2.1 73M1906B 20-Pin TSSOP Pinout............................................................................................ 8
2.2 73M1916 20-Pin TSSOP Pinout .............................................................................................. 9
2.3 73M1906B 32-Pin QFN Pinout .............................................................................................. 10
2.4 73M1916 32-Pin QFN Pinout ................................................................................................ 12
2.5 73M1866B Pinout ................................................................................................................. 14
2.6 Requisite Use of Exposed Bottom Pad on 73M1866B and 73M1966B QFN Packages .......... 15
Electrical Characteristics and Specifications............................................................................. 16
3.1 Isolation Barrier Characteristics ............................................................................................. 16
3.2 Electrical Specifications......................................................................................................... 16
3.2.1 Absolute Maximum Ratings ....................................................................................... 16
3.2.2 Recommended Operating Conditions ........................................................................ 16
3.2.3 DC Characteristics..................................................................................................... 17
3.3 Interface Timing Specification................................................................................................ 18
3.3.1 SPI Interface ............................................................................................................. 18
3.3.2 PCM Highway Interface ............................................................................................. 19
3.4 Analog Specifications ............................................................................................................ 20
3.4.1 DC Specifications ...................................................................................................... 20
3.4.2 Call Progress Monitor ................................................................................................ 21
3.5 73M1x66B Line-Side Electrical Specifications (73M1916)...................................................... 22
3.6 Reference and Regulation ..................................................................................................... 23
3.7 DC Transfer Characteristics .................................................................................................. 23
3.8 Transmit Path ....................................................................................................................... 24
3.9 Receive Path ........................................................................................................................ 25
3.10 Transmit Hybrid Cancellation ................................................................................................ 26
3.11 Receive Notch Filter .............................................................................................................. 26
3.12 Detectors .............................................................................................................................. 27
3.12.1 Over-Voltage Detector ............................................................................................... 27
3.12.2 Over-Current Detector ............................................................................................... 27
3.12.3 Under-Voltage Detector ............................................................................................. 27
3.12.4 Over-Load Detector ................................................................................................... 27
Applications Information ............................................................................................................. 28
4.1 Example Schematic of the 73M1966B and 73M1866B .......................................................... 28
4.2 Bill of Materials...................................................................................................................... 30
4.3 Over-Voltage and EMI Protection .......................................................................................... 31
4.4 Isolation Barrier Pulse Transformer ....................................................................................... 32
SPI Interface................................................................................................................................. 33
Control and Status Registers ...................................................................................................... 37
Hardware Control Functions ....................................................................................................... 41
7.1 Device Revision .................................................................................................................... 41
7.2 Interrupt Control .................................................................................................................... 41
7.3 Power Management .............................................................................................................. 42
7.4 Device Clock Management.................................................................................................... 42
7.5 GPIO Registers ..................................................................................................................... 43
7.6 Call Progress Monitor ............................................................................................................ 44
7.7 16 kHz Operation of Call Progress Monitor ............................................................................ 44
7.8 Device Reset ........................................................................................................................ 44
PCM Highway Interface and Signal Processing ......................................................................... 45
8.1 PCM Highway Interface Timing ............................................................................................. 45
8.2 PCM Clock Frequencies........................................................................................................ 47
8.3 Master Mode ......................................................................................................................... 47
8.4 A-law
/ μ-law
Compander ...................................................................................................... 47
Rev. 1.6
3
4
5
6
7
8
2
DS_1x66B_001
8.5
73M1866B/73M1966B Data Sheet
9
10
Transmit and Receive Levels ................................................................................................ 48
8.5.1 A-Law........................................................................................................................ 48
8.5.2
μ-Law
........................................................................................................................ 48
8.5.3 Transmit and Receive Level Control .......................................................................... 48
8.6 Transmit Path Signal Processing........................................................................................... 49
8.6.1 General Description ................................................................................................... 49
8.6.2 Total Transmit Path Response................................................................................... 49
8.6.3 73M1x66B Transmit Spectrum................................................................................... 50
8.7 Receive Path Signal Processing............................................................................................ 50
8.7.1 General Description ................................................................................................... 50
8.7.2 Total Receive Path Response.................................................................................... 51
8.7.3 Receiver DC Offset Subtraction ................................................................................. 51
8.8 PCM Control Functions ......................................................................................................... 52
8.8.1 Transmit and Receive Level Control .......................................................................... 57
8.8.2 Time Slot Assignment Example ................................................................................. 59
Barrier Information ...................................................................................................................... 60
9.1 Isolation Barrier ..................................................................................................................... 60
9.2 Barrier Powered Options ....................................................................................................... 60
9.2.1 Barrier Powered Operation ........................................................................................ 60
9.2.2 Line Powered Operation ............................................................................................ 60
9.3 Synchronization of the Barrier ............................................................................................... 60
9.4 Auto-Poll ............................................................................................................................... 61
9.5 Barrier Control Functions ...................................................................................................... 61
9.6 Line-Side Device Operating Modes ....................................................................................... 63
9.7 Fail-Safe Operation of Line-Side Device ................................................................................ 63
Configurable Direct Access Arrangement (DAA) ....................................................................... 64
10.1 Pulse Dialing ......................................................................................................................... 64
10.2 DC Termination ..................................................................................................................... 64
10.3 AC Termination ..................................................................................................................... 66
10.4 Billing Tone Rejection ........................................................................................................... 67
10.5 Trans-Hybrid Cancellation ..................................................................................................... 68
10.6 Direct Access Arrangement Control Functions....................................................................... 68
10.7 International Register Settings Table for DC and AC Terminations ........................................ 72
Line Sensing and Status ............................................................................................................. 73
11.1 Auxiliary A/D Converter ......................................................................................................... 73
11.2 Ring Detection ...................................................................................................................... 73
11.3 Line In Use Detection (LIU) ................................................................................................... 73
11.4 Parallel Pick Up (PPU) .......................................................................................................... 73
11.5 Polarity Reversal Detection ................................................................................................... 73
11.6 Off-hook Detection of Caller ID Type II .................................................................................. 73
11.7 Voltage and Current Detection .............................................................................................. 74
11.8 Under Voltage Detection (UVD)............................................................................................. 74
11.9 Over Voltage Detection (OVD) .............................................................................................. 74
11.10 AC Signal Overload Detection ............................................................................................. 74
11.11 Over Current Detection (OID).............................................................................................. 74
11.12 Line Sensing Control Functions........................................................................................... 75
Loopback and Testing Modes ..................................................................................................... 78
Performance ................................................................................................................................ 80
13.1 Transmit................................................................................................................................ 80
13.2 Receive................................................................................................................................. 82
Package Layout ........................................................................................................................... 85
Ordering Information ................................................................................................................... 87
Contact Information..................................................................................................................... 87
11
12
13
14
15
16
Revision History .................................................................................................................................. 88
Rev. 1.6
3
73M1866B/73M1966B Data Sheet
DS_1x66B_001
Figures
Figure 1: Simple 73M1x66B Reference Block Diagram ............................................................................ 6
Figure 2: 73M1906B 20-Pin TSSOP Pinout.............................................................................................. 8
Figure 3: 73M1916 20-Pin TSSOP Pinout ................................................................................................ 9
Figure 4: 73M1906B 32-Pin QFN Pinout ................................................................................................ 10
Figure 5: 73M1916 32-Pin QFN Pinout .................................................................................................. 12
Figure 6: 73M1866B 42-Pin Pinout ........................................................................................................ 14
Figure 7: SPI Timing Diagram ................................................................................................................ 18
Figure 8: PCM Timing Diagram for Positive Edge Transmit Mode and Negative Edge Receive Mode ..... 19
Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode ..... 20
Figure 10: Frequency Response of the Call Progress Monitor Filter ....................................................... 21
Figure 11: Demo Board Circuit Connecting AOUT to a Speaker ............................................................. 21
Figure 12: Recommended Circuit for the 73M1966B .............................................................................. 28
Figure 13: Recommended Circuit for the 73M1866B .............................................................................. 29
Figure 14: Suggested Over-Voltage Protection and EMI Suppression Circuit ......................................... 31
Figure 15: Daisy-Chain Configuration .................................................................................................... 34
Figure 16: SPI Write Operation – 8-bit Mode .......................................................................................... 34
Figure 17: SPI Read Transaction – 8-bit Mode....................................................................................... 35
Figure 18: SPI Write Transaction – 16-bit Mode ..................................................................................... 35
Figure 19: SPI Read Transaction – 16-bit Mode..................................................................................... 35
Figure 20: 8-bit Transmission Example .................................................................................................. 45
Figure 21: 16-bit Transmission Example ................................................................................................ 46
Figure 22: Example of PCM Highway Interconnect................................................................................. 46
Figure 23: Example of PCM Highway Interconnect for Typical Large Systems ....................................... 46
Figure 24: Mapping of A-law Code to 16-bit Code .................................................................................. 48
Figure 25: Mapping of μ-law
Code to 16-bit Code .................................................................................. 48
Figure 26: Transmit Path Overall Frequency Response to Fs of 8 kHz ................................................... 49
Figure 27: Transmit Path Passband Response for an 8 kHz Sample Rate.............................................. 49
Figure 28: Transmit Spectrum to 32 kHz for an 8 kHz Sample Rate ....................................................... 50
Figure 29: Overall Frequency Response of the Receive Path ................................................................. 51
Figure 30: Pass-band Response of the Overall Receive Path................................................................. 51
Figure 31: Timing Relationships with Various TTS, TCS, TPOL, and RTS, RCS, RPOL Settings............ 59
Figure 32: Line-Side Device AC and DC Circuits.................................................................................... 63
Figure 33: DC-IV Characteristics............................................................................................................ 64
Figure 34: Tip-Ring Voltage versus Current Using Different DCIV Settings............................................. 65
Figure 35: Voltage versus Current in the Seize Mode is the Same for All DCIV Settings ......................... 66
Figure 36: Magnitude Response of Impedance Matching Filter, ACZ (3:0)=0010 (ES 203 021-2) ........... 67
Figure 37: Magnitude Response of Billing Tone Notch Filter .................................................................. 67
Figure 38: Trans-hybrid Cancellation ..................................................................................................... 68
Figure 39: Loopback Modes Highlighted ................................................................................................ 78
Figure 40: Variation of Transmit Gain Digital Input to Analog Output at the Line ..................................... 80
Figure 41: Gain versus Frequency for Digital Input to Analog Output at the Line..................................... 81
Figure 42: Signal to Total Distortion versus Input Level for Digital Input to Analog Output to the Line...... 81
Figure 43: Variation of Receiver Analog Gain at the Line to the Digital DX Output .................................. 82
Figure 44: Gain versus Frequency for Analog Input at the Line to the Digital DX Output ......................... 83
Figure 45: Signal to Total Distortion versus Input Level for Analog at the Line to the Digital DX Output... 83
Figure 46: Return Loss, @ 80 mA .......................................................................................................... 84
Figure 47: 20-Pin TSSOP Package Dimensions..................................................................................... 85
Figure 48: 32-Pin QFN Package Dimensions ......................................................................................... 85
Figure 49: 42-Pin QFN Package Dimensions ......................................................................................... 86
4
Rev. 1.6
DS_1x66B_001
73M1866B/73M1966B Data Sheet
Tables
Table 1: 73M1906B 20-Pin TSSOP Pin Definitions .................................................................................. 8
Table 2: 73M1916 20-Pin TSSOP Pin Definitions ..................................................................................... 9
Table 3: 73M1906B 32-Pin QFN Pin Definitions ..................................................................................... 10
Table 4: 73M1916 32-Pin QFN Pin Definitions ....................................................................................... 12
Table 5: 73M1866B Pin Definitions ........................................................................................................ 14
Table 6: Isolation Barrier Characteristics ................................................................................................ 16
Table 7: Absolute Maximum Device Ratings .......................................................................................... 16
Table 8: Recommended Operating Conditions ....................................................................................... 16
Table 9: DC Characteristics ................................................................................................................... 17
Table 10: SPI Interface Switching Characteristics .................................................................................. 18
Table 11: Switching Characteristics – PCM Interface (Slave Mode) ........................................................ 19
Table 12: Switching Characteristics – PCM Interface (Master Mode) ...................................................... 19
Table 13: Reference Voltage Specifications ........................................................................................... 20
Table 14: Component Values for the Speaker Driver .............................................................................. 21
Table 15: Call Progress Monitor Specification ........................................................................................ 22
Table 16: Line-Side Absolute Maximum Ratings .................................................................................... 22
Table 17: VBG Specifications ................................................................................................................ 23
Table 18: Maximum DC Transmit Levels ................................................................................................ 23
Table 19: Transmit Path......................................................................................................................... 24
Table 20: Receive Path ......................................................................................................................... 25
Table 21: Transmit Hybrid Cancellation Characteristics .......................................................................... 26
Table 22: Receive Notch Filter ............................................................................................................... 26
Table 23: Over-voltage Detector ............................................................................................................ 27
Table 24: Over-current Detector............................................................................................................. 27
Table 25: Under-voltage Detector .......................................................................................................... 27
Table 26: Over-load Detector ................................................................................................................. 27
Table 27: Reference Bill of Materials for 73M1x66B ............................................................................... 30
Table 28: Reference Bill of Materials for Figure 14 ................................................................................. 31
Table 29: Compatible Pulse Transformer Sources ................................................................................. 32
Table 30: Pulse Transformer Electrical Characteristics ........................................................................... 32
Table 31: Control and Status Register Map ............................................................................................ 37
Table 32: Alphabetical Bit Map .............................................................................................................. 38
Table 33: PCM Control Functions .......................................................................................................... 52
Table 34: Transmit Gain Control ............................................................................................................ 57
Table 35: Recommended Gain Setting................................................................................................... 57
Table 36: Receive Gain Control ............................................................................................................. 59
Table 37: Barrier Control Functions........................................................................................................ 61
Table 38: DAA Control Functions ........................................................................................................... 68
Table 39: Recommended Register Settings for International Compatibility ............................................. 72
Table 40: Line Sensing Control Functions .............................................................................................. 75
Table 41: Loopback Modes.................................................................................................................... 78
Table 42: Loopback Modes Summary .................................................................................................... 79
Table 43: Order Numbers and Packaging Marks .................................................................................... 87
Rev. 1.6
5
