SL74LS06
Hex Inverted Buffers with
Open-Collector Outputs
This device contains hex inverted buffers with open-collector. It
performs the Boolean function Y=A in positive Logic.
•
High Output Voltage (30 V)
•
High Speed ( t
PD
= 8.5 ns typical)
•
Low Power Dissipation (P
D
= 18 mW per Gate)
ORDERING INFORMATION
SL74LS06N Plastic
SL74LS06D SOIC
T
A
= 0° to 70° C for all
packages
LOGIC DIAGRAM
PIN ASSIGNMENT
A1
1
2
Y1
A2
3
4
Y2
A3
5
6
Y3
A4
9
8
Y4
A5
11
10
Y5
FUNCTION TABLE
Inputs
A
H
Output
Y
L
H
A6
13
12
Y6
PIN 14 =V
CC
PIN 7 = GND
L
SLS
System Logic
Semiconductor
SL74LS06
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
Tstg
*
Parameter
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Value
7.0
5.5
30
-65 to +150
Unit
V
V
V
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IH
V
IL
V
OH
I
OL
T
A
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Current
Ambient Temperature Range
0
Parameter
Min
4.75
2.0
0.8
30
40
+70
Max
5.25
Unit
V
V
V
V
mA
°C
DC ELECTRICAL CHARACTERISTICS
over full operating conditions
Guaranteed Limit
Symbol
V
IK
I
OH
V
OL
Parameter
Input Clamp Voltage
High Level Output Current
Low Level Output Voltage
Test Conditions
V
CC
= min, I
IN
= -18 mA
V
CC
= min, V
OH
= max
V
CC
= min, I
OL
= 16 mA
V
CC
= min, I
OL
= 40 mA
I
IH
High Level Input Current
V
CC
= max, V
IN
= 2.7 V
V
CC
= max, V
IN
= 5.5 V
I
IL
I
CC
Low Level Input Current
Supply Current
V
CC
= max, V
IN
= 0.4 V
V
CC
= max
Total with
outputs high
Total with
outputs low
Min
Max
-1.5
250
0.4
0.7
20
1
-0.2
18
60
µA
mA
mA
mA
Unit
V
µA
V
SLS
System Logic
Semiconductor
SL74LS06
AC ELECTRICAL CHARACTERISTICS
(T
A
= 25°C, V
CC
= 5.0 V, C
L
= 15 pF,
R
L
= 110
Ω,
t
r
= 15 ns, t
f
= 6.0 ns)
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay, Input A to Output Y
Propagation Delay, Input A to Output Y
Min
Max
15
20
Unit
ns
ns
Figure 1. Switching Waveforms
NOTE A. C
L
includes probe and jig capacitance.
Figure 2. Test Circuit
SLS
System Logic
Semiconductor
