INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT393
Dual 4-bit binary ripple counter
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
FEATURES
•
Two 4-bit binary counters with individual clocks
•
Divide-by any binary module up to 28 in one package
•
Two master resets to clear each 4-bit counter
individually
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT393 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT393
The 74HC/HCT393 are 4-bit binary ripple counters with
separate clocks (1CP and 2 CP) and master reset (1MR
and 2MR) inputs to each counter. The operation of each
half of the “393” is the same as the “93” except no external
clock connections are required.
The counters are triggered by a HIGH-to-LOW transition of
the clock inputs. The counter outputs are internally
connected to provide clock inputs to succeeding stages.
The outputs of the ripple counter do not change
synchronously and should not be used for high-speed
address decoding.
The master resets are active-HIGH asynchronous inputs
to each 4-bit counter identified by the “1” and “2” in the pin
description.
A HIGH level on the nMR input overrides the clock and
sets the outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nCP to nQ
0
nQ to nQ
n+1
nMR to nQ
n
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency
input capacitance
power dissipation capacitance per counter
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
12
5
11
99
3.5
23
20
6
15
53
3.5
25
ns
ns
ns
MHz
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
PIN DESCRIPTION
PIN NO.
1, 13
2, 12
3, 4, 5, 6, 11, 10, 9, 8
7
14
SYMBOL
1CP, 2CP
1MR, 2MR
1Q
0
to 1Q
3
, 2Q
0
to 2Q
3
GND
V
CC
NAME AND FUNCTION
74HC/HCT393
clock inputs (HIGH-to-LOW, edge-triggered)
asynchronous master reset inputs (active HIGH)
flip-flop outputs
ground (0 V)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
74HC/HCT393
Fig.4 Functional diagram.
Fig.5 State diagram.
COUNT SEQUENCE FOR 1 COUNTER
OUTPUTS
COUNT
Q
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Notes
Fig.6 Logic diagram (one counter).
1. H = HIGH voltage level
L = LOW voltage level
4
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Q
1
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Q
2
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Q
3
December 1990
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
74HC/HCT393
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.7
+25
−40
to
+85
max.
155
31
26
55
11
9
175
35
30
95
19
16
100
20
17
100
20
17
5
5
5
5
24
28
−40
to
+125
min. max.
190
38
32
70
14
12
210
42
36
110
22
19
120
24
20
120
24
20
5
5
5
4
20
24
min. typ. max. min.
t
PHL
/ t
PLH
propagation delay
nCP to nQ
0
t
PHL
/ t
PLH
propagation delay
nQ
n
to nQ
n+1
t
PHL
propagation delay
nMR to nQ
n
41
15
12
14
5
4
39
14
11
19
7
6
80
16
14
80
16
14
5
5
5
6
30
35
17
6
5
19
7
6
3
1
1
30
90
107
125
25
21
45
9
8
140
28
24
75
15
13
ns
Fig.7
ns
Fig.8
t
THL
/ t
TLH
output transition time
ns
Fig.7
t
W
clock pulse width
HIGH or LOW
master reset pulse
width; HIGH
removal time
nMR to nCP
maximum clock pulse
frequency
ns
Fig.7
t
W
ns
Fig.8
t
rem
ns
Fig.8
f
max
MHz
Fig.7
December 1990
5
