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74HCT161PW

Counter ICs SYNC 4-BIT BINARY COUNTER

器件类别：逻辑    逻辑   

厂商名称：NXP(恩智浦)

厂商官网：https://www.nxp.com

器件标准：

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器件：74HCT161PW

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
NXP(恩智浦)
零件包装代码
TSSOP
包装说明
SOT403-1, TSSOP-16
针数
16
Reach Compliance Code
unknown
其他特性
TCO OUTPUT
计数方向
UP
系列
HCT
JESD-30 代码
R-PDSO-G16
JESD-609代码
e4
长度
5 mm
负载电容（CL）
50 pF
负载/预设输入
YES
逻辑集成电路类型
BINARY COUNTER
最大频率@ Nom-Sup
18000000 Hz
最大I（ol）
0.004 A
工作模式
SYNCHRONOUS
湿度敏感等级
1
位数
4
功能数量
1
端子数量
16
最高工作温度
125 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
TSSOP16,.25
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）
260
电源
5 V
传播延迟（tpd）
65 ns
认证状态
Not Qualified
座面最大高度
1.1 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
AUTOMOTIVE
端子面层
NICKEL PALLADIUM GOLD
端子形式
GULL WING
端子节距
0.65 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
触发器类型
POSITIVE EDGE
宽度
4.4 mm
最小 fmax
15 MHz
Base Number Matches
1
文档预览
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT161
Presettable synchronous 4-bit
binary counter; asynchronous reset
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
FEATURES
•
Synchronous counting and loading
•
Two count enable inputs for n-bit cascading
•
Positive-edge triggered clock
•
Asynchronous reset
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT161 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT161 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q
0
to Q
3
) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
74HC/HCT161
input (PE) disables the counting action and causes the
data at the data inputs (D
0
to D
3
) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q
0
to Q
3
) to LOW level regardless
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q
0
. This
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
1
-
f
max
= --------------------------------------------------------------------------------------------------
t
P(max)
(CP to TC)
+
t
SU
(CEP to CP)
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL PARAMETER
t
PHL
/ t
PLH
propagation delay
CP to Q
n
CP to TC
MR to Q
n
MR to TC
CET to TC
maximum clock frequency
input capacitance
power dissipation
capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF;
V
CC
= 5 V
19
21
20
20
10
44
3.5
33
HCT
20
24
25
26
14
45
3.5
35
ns
ns
ns
ns
ns
MHz
pF
pF
UNIT
Notes
1. C
PD
is used to determine the
dynamic power dissipation
(P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
)
where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of
outputs
C
L
= output load capacitance in
pF
V
CC
= supply voltage in V
2. For HC the condition is
V
I
= GND to V
CC
For HCT the condition is
V
I
= GND to V
CC
−
1.5 V
f
max
C
I
C
PD
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
SYMBOL
MR
CP
D
0
to D
3
CEP
GND
PE
CET
Q
0
to Q
3
TC
V
CC
NAME AND FUNCTION
asynchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data inputs
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop outputs
terminal count output
positive supply voltage
74HC/HCT161
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
OPERATING MODE
MR
reset (clear)
parallel load
count
hold
(do nothing)
Note
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑
= LOW-to-HIGH CP transition
L
H
H
H
H
H
X
↑
↑
↑
X
X
CP
X
X
X
h
I
X
CEP
X
X
X
h
X
I
CET
X
I
I
h
h
h
PE
X
I
h
X
X
X
D
n
L
L
H
count
q
n
q
n
Q
n
L
L
(1)
(1)
(1)
OUTPUTS
TC
L
December 1990
4
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
Fig.5 State diagram.
Fig.6
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen,
zero, one and two; inhibit.
December 1990
5
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参数对比
与74HCT161PW相近的元器件有：74HC161D-AUJ、74HC161PW-T、74HCT161D-T、74HCT161N、74HC161DB-T、74HCT161DB。描述及对比如下：
型号 74HCT161PW 74HC161D-AUJ 74HC161PW-T 74HCT161D-T 74HCT161N 74HC161DB-T 74HCT161DB
描述 Counter ICs SYNC 4-BIT BINARY COUNTER Counter ICs Presettable synchrns 4-bit binary counter Counter ICs SYNC 4-BIT BINARY COUNTER Counter ICs SYNC 4-BIT BINARY COUNTER Counter ICs SYNC 4-BIT BINARY COUNTER Counter ICs SYNC 4-BIT BINARY COUNTER Counter ICs SYNC 4-BIT BINARY COUNTER
是否Rohs认证 符合 - 符合 符合 符合 符合 符合
厂商名称 NXP(恩智浦) - NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦)
零件包装代码 TSSOP - TSSOP SOIC DIP SOIC SOIC
包装说明 SOT403-1, TSSOP-16 - TSSOP, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16 DIP, DIP16,.3 SSOP, SOT338-1, SSOP-16
针数 16 - 16 16 16 16 16
Reach Compliance Code unknown - unknown unknown unknown unknown unknown
其他特性 TCO OUTPUT - TCO OUTPUT TCO OUTPUT TCO OUTPUT TCO OUTPUT TCO OUTPUT
计数方向 UP - UP UP UP UP UP
系列 HCT - HC/UH HCT HCT HC/UH HCT
JESD-30 代码 R-PDSO-G16 - R-PDSO-G16 R-PDSO-G16 R-PDIP-T16 R-PDSO-G16 R-PDSO-G16
JESD-609代码 e4 - e4 e4 e4 e4 e4
长度 5 mm - 5 mm 9.9 mm 21.6 mm 6.2 mm 6.2 mm
负载电容（CL） 50 pF - 50 pF 50 pF 50 pF 50 pF 50 pF
负载/预设输入 YES - YES YES YES YES YES
逻辑集成电路类型 BINARY COUNTER - BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER
工作模式 SYNCHRONOUS - SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
湿度敏感等级 1 - 1 1 - 1 1
位数 4 - 4 4 4 4 4
功能数量 1 - 1 1 1 1 1
端子数量 16 - 16 16 16 16 16
最高工作温度 125 °C - 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -40 °C - -40 °C -40 °C -40 °C -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP - TSSOP SOP DIP SSOP SSOP
封装形状 RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE IN-LINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度） 260 - 260 260 NOT APPLICABLE 260 260
传播延迟（tpd） 65 ns - 285 ns 65 ns 65 ns 57 ns 65 ns
认证状态 Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.1 mm - 1.1 mm 1.75 mm 4.7 mm 2 mm 2 mm
最大供电电压 (Vsup) 5.5 V - 6 V 5.5 V 5.5 V 6 V 5.5 V
最小供电电压 (Vsup) 4.5 V - 2 V 4.5 V 4.5 V 2 V 4.5 V
标称供电电压 (Vsup) 5 V - 5 V 5 V 5 V 5 V 5 V
表面贴装 YES - YES YES NO YES YES
技术 CMOS - CMOS CMOS CMOS CMOS CMOS
温度等级 AUTOMOTIVE - AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
端子面层 NICKEL PALLADIUM GOLD - NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD
端子形式 GULL WING - GULL WING GULL WING THROUGH-HOLE GULL WING GULL WING
端子节距 0.65 mm - 0.65 mm 1.27 mm 2.54 mm 0.65 mm 0.65 mm
端子位置 DUAL - DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 - 30 30 NOT APPLICABLE 30 30
触发器类型 POSITIVE EDGE - POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
宽度 4.4 mm - 4.4 mm 3.9 mm 7.62 mm 5.3 mm 5.3 mm
最小 fmax 15 MHz - 15 MHz 15 MHz 15 MHz 15 MHz 15 MHz
Base Number Matches 1 - 1 1 1 1 1
Source Url Status Check Date - - 2013-06-14 00:00:00 2013-06-14 00:00:00 2013-06-14 00:00:00 2013-06-14 00:00:00 -
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器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
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