74HC2G00-Q100;
74HCT2G00-Q100
Dual 2-input NAND gate
Rev. 2 — 20 November 2018
Product data sheet
1. General description
The 74HC2G00-Q100; 74HCT2G00-Q100 is a dual 2-input NAND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of
V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
•
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 6.0 V
Input levels:
•
For 74HC2G00-Q100: CMOS level
•
For 74HCT2G00-Q100: TTL level
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
•
MIL-STD-883, method 3015 exceeds 2000 V
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)
•
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC2G00DP-Q100
74HCT2G00DP-Q100
74HC2G00DC-Q100
74HCT2G00DC-Q100
-40 °C to +125 °C
VSSOP8
-40 °C to +125 °C
Name
TSSOP8
Description
plastic thin shrink small outline package;
8 leads; body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
Version
SOT505-2
SOT765-1
Nexperia
74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
4. Marking
Table 2. Marking code
Type number
74HC2G00DP-Q100
74HCT2G00DP-Q100
74HC2G00DC-Q100
74HCT2G00DC-Q100
[1]
Marking code[1]
H00
T00
H00
T00
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1
2
5
6
1A
1B
2A
2B
1Y
2Y
mna712
7
3
2
&
7
B
5
6
&
mna713
3
A
Y
mna099
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
Logic diagram (one driver)
6. Pinning information
6.1. Pinning
74HC2G00
74HCT2G00
1A
1B
2Y
GND
1
2
3
4
001aai255
8
7
6
5
V
CC
1Y
2B
2A
Fig. 4.
Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
6.2. Pin description
Table 3. Pin description
Symbol
1A, 2A
1B, 2B
GND
1Y, 2Y
V
CC
Pin
1, 5
2, 6
4
7, 3
8
Description
data input
data input
ground (0 V)
data output
supply voltage
74HC_HCT2G00_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 20 November 2018
2 / 11
Nexperia
74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
nA
L
L
H
H
nB
L
H
L
H
Output
nY
H
H
H
L
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
D
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
dynamic power dissipation
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
V
O
= -0.5 V to (V
CC
+ 0.5 V)
[1]
[1]
[1]
[1]
[1]
T
amb
= -40 °C to +125 °C
[2]
Min
-0.5
-
-
-
-
-50
-65
-
Max
+7.0
±20
±20
25
50
-
+150
300
Unit
V
mA
mA
mA
mA
mA
°C
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 package: above 55 °C the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of P
tot
derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and V
CC
= 2.0 V
fall rate
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC2G00-Q100
Min
2.0
0
0
-40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT2G00-Q100
Min
4.5
0
0
-40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
°C
ns/V
ns/V
ns/V
Unit
74HC_HCT2G00_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 20 November 2018
3 / 11
Nexperia
74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
10. Static characteristics
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V). All typical values are measured at T
amb
= 25 °C.
Symbol
Parameter
Conditions
-40 °C to +85 °C
Min
74HC2G00-Q100
V
IH
HIGH-level input
voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level input
voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
= -20 μA; V
CC
= 2.0 V
I
O
= -20 μA; V
CC
= 4.5 V
I
O
= -20 μA; V
CC
= 6.0 V
I
O
= -4.0 mA; V
CC
= 4.5 V
I
O
= -5.2 mA; V
CC
= 6.0 V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 20 μA; V
CC
= 2.0 V
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 20 μA; V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
V
IH
V
IL
V
OH
input leakage current
supply current
input capacitance
HIGH-level input
voltage
LOW-level input
voltage
HIGH-level output
voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
V
I
= V
IH
or V
IL
I
O
= -20 μA; V
CC
= 4.5 V
I
O
= -4.0 mA; V
CC
= 4.5 V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
I
I
CC
ΔI
CC
C
I
input leakage current
supply current
additional supply
current
input capacitance
V
I
= V
CC
or GND; V
CC
= 5.5 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input; V
CC
= 4.5 V to 5.5 V;
V
I
= V
CC
- 2.1 V; I
O
= 0 A
-
-
-
-
-
-
0
0.15
-
-
-
1.5
0.1
0.33
±1.0
10
375
-
-
-
-
-
-
-
0.1
0.4
±1.0
20
410
-
V
V
μA
μA
μA
pF
4.4
4.13
4.5
4.32
-
-
4.4
3.7
-
-
V
V
V
I
= V
CC
or GND; V
CC
= 6.0 V
per input pin; V
I
= V
CC
or GND;
I
O
= 0 A; V
CC
= 6.0 V
-
-
-
-
-
-
-
-
2.0
-
0
0
0
0.15
0.16
-
-
1.5
1.6
1.2
0.1
0.1
0.1
0.33
0.33
±1.0
10
-
-
0.8
-
-
-
-
-
-
-
-
2.0
-
0.1
0.1
0.1
0.4
0.4
±1.0
20
-
-
0.8
V
V
V
V
V
μA
μA
pF
V
V
1.9
4.4
5.9
4.13
5.63
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Typ
Max
-40 °C to +125 °C
Min
Max
Unit
74HCT2G00-Q100
74HC_HCT2G00_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 20 November 2018
4 / 11
Nexperia
74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); all typical values are measured at T
amb
= 25 °C; for test circuit see
Fig. 6.
Symbol Parameter
74HC2G00-Q100
t
pd
propagation delay nA and nB to nY; see
Fig. 5
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
t
t
transition time
see
Fig. 5
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
C
PD
power dissipation V
I
= GND to V
CC
capacitance
propagation delay nA and nB to nY; see
Fig. 5
V
CC
= 4.5 V
t
t
C
PD
[1]
[2]
[3]
Conditions
-40 °C to +85 °C
Min
[1]
-
-
-
[2]
-
-
-
[3]
-
18
6
5
10
95
19
16
-
25
9
7
95
19
16
Typ
Max
-40 °C to +125 °C Unit
Min
Max
-
-
-
-
-
-
-
110
22
20
125
25
20
-
ns
ns
ns
ns
ns
ns
pF
74HCT2G00-Q100
t
pd
[1]
-
[2]
[3]
-
-
12
6
10
24
19
-
-
-
-
29
22
-
ns
ns
pF
transition time
V
CC
= 4.5 V; see
Fig. 5
power dissipation V
I
= GND to V
CC
- 1.5 V
capacitance
t
pd
is the same as t
PLH
and t
PHL
.
t
t
is the same as t
TLH
and t
THL
.
C
PD
is used to determine the dynamic power dissipation (P
D
in μW).
2
2
P
D
= C
PD
x V
CC
x f
i
x N + Σ(C
L
x V
CC
x f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
2
Σ(C
L
x V
CC
x f
o
) = sum of outputs.
74HC_HCT2G00_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 20 November 2018
5 / 11
