74LVC2G32
Dual 2-input OR gate
Rev. 13 — 3 July 2017
Product data sheet
1
General description
The 74LVC2G32 provides a 2-input OR gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
these devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2
Features and benefits
•
•
•
•
•
•
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs in the Power-down mode
High noise immunity
±24 mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Complies with JEDEC standard:
–
JESD8-7 (1.65 V to 1.95 V)
–
JESD8-5 (2.3 V to 2.7 V)
–
JESD8-B/JESD36 (2.7 V to 3.6 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
–
HBM JESD22-A114F exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
•
•
•
•
3
Ordering information
Package
Temperature
range
Name
TSSOP8
VSSOP8
Table 1. Ordering information
Type number
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
74LVC2G32DP
74LVC2G32DC
-40 °C to +125 °C
-40 °C to +125 °C
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
Nexperia
74LVC2G32
Package
Temperature
range
Name
XSON8
XSON8
XQFN8
XSON8
XSON8
X2SON8
Dual 2-input OR gate
Type number
Description
Version
74LVC2G32GT
74LVC2G32GF
74LVC2G32GM
74LVC2G32GN
74LVC2G32GS
74LVC2G32GX
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 x 1.95 x 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
plastic thermal enhanced extremely thin small outline
package; no leads; 8 terminals;
body 1.35 x 0.8 x 0.35 mm
SOT1089
SOT902-2
SOT1116
SOT1203
SOT1233
4
Marking
Marking code
V32
V32
V32
VG
V32
VG
VG
VG
[1]
Table 2. Marking codes
Type number
74LVC2G32DP
74LVC2G32DC
74LVC2G32GT
74LVC2G32GF
74LVC2G32GM
74LVC2G32GN
74LVC2G32GS
74LVC2G32GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC2G32
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 13 — 3 July 2017
2 / 21
Nexperia
74LVC2G32
Dual 2-input OR gate
5
Functional diagram
≥1
1A
1B
2A
2B
1Y
2Y
≥1
001aah791
001aah792
Figure 1. Logic symbol
B
Figure 2. IEC logic symbol
Y
A
mna166
Figure 3. Logic diagram (one gate)
6
Pinning information
6.1 Pinning
74LVC2G32
1A
1
8
V
CC
1B
2
7
1Y
74LVC2G32
1A
1B
2Y
GND
1
2
3
4
001aab742
2Y
8
7
6
5
V
CC
1Y
2B
2A
3
6
2B
GND
4
5
2A
001aab743
Transparent top view
Figure 4. Pin configuration SOT505-2 and SOT765-1
Figure 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC2G32
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 13 — 3 July 2017
3 / 21
Nexperia
74LVC2G32
74LVC2G32
Dual 2-input OR gate
terminal 1
index area
1Y
1
V
CC
7
1A
74LVC2G32
1A 1
7
8
V
CC
1B
2
4
GND
2Y
3
5
aaa-027038
8
1Y
2B
2
6
1B
6
2B
4
2A
3
5
2Y
GND
2A
001aae994
Transparent top view
Transparent top view
Figure 6. Pin configuration SOT902-2
Figure 7. Pin configuration SOT1233
6.2 Pin description
Table 3. Pin description
Symbol
Pin
SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT1116,
SOT1203 and SOT1233
SOT902-2
7, 3
6, 2
4
1, 5
8
Description
1A, 2A
1B, 2B
GND
1Y, 2Y
V
CC
1, 5
2, 6
4
7, 3
8
data input
data input
ground (0 V)
data output
supply voltage
7
Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
nA
L
L
H
H
Output
nB
L
H
L
H
nY
L
H
H
H
74LVC2G32
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 13 — 3 July 2017
4 / 21
Nexperia
74LVC2G32
Dual 2-input OR gate
8
Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
Parameter
supply voltage
input voltage
output voltage
Conditions
[1]
Min
-0.5
-0.5
-0.5
-0.5
-50
-
-
-
-100
-65
[3]
[1]
[2]
Max
+6.5
+6.5
V
CC
+ 0.5
+6.5
-
±50
±50
100
-
+150
300
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
mW
Active mode
Power-down mode
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
V
I
< 0 V
V
O
< 0 V or V
O
> V
CC
V
O
= 0 V to V
CC
T
amb
= -40 °C to +125 °C
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition.
For TSSOP8 package: above 55 °C the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of P
tot
derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 118 °C the value of P
tot
derates linearly with 7.8 mW/K.
For X2SON8 package: above 118 °C the value of P
tot
derates linearly with 7.7 mW/K.
9
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode
Table 6. Operating conditions
Symbol
V
CC
V
I
V
O
T
amb
Δt/ΔV
Conditions
Min
1.65
0
0
0
-40
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74LVC2G32
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 13 — 3 July 2017
5 / 21
FPGA/CPLD
