74LVC38A
Quad 2-input NAND gate; open-drain
Rev. 4 — 4 November 2011
Product data sheet
1. General description
The 74LVC38A provides four 2-input NAND functions. The outputs are open-drain and
can be connected to other open-drain outputs to implement active-LOW wired-OR or
active-HIGH wired-AND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Open-drain outputs
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V
JESD8-5A (2.3 V to 2.7 V
JESD8-C/JESD36 (2.7 V to 3.6 V
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC38AD
74LVC38ADB
74LVC38APW
74LVC38ABQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
NXP Semiconductors
74LVC38A
Quad 2-input NAND gate; open-drain
4. Functional diagram
1
2
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
5
2Y
6
9
3Y
8
10
&
8
&
3
&
6
4Y
11
12
13
&
11
mna697
mna698
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Y
A
B
GND
mna699
Fig 3.
Logic diagram for one gate
5. Pinning information
5.1 Pinning
74LVC38A
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aad038
74LVC38A
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
terminal 1
index area
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
GND
3Y
8
GND
(1)
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
1A
1
001aad039
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
74LVC38A
Pin configuration for SO14 and (T)SSOP14
Fig 5.
Pin configuration for DHVQFN14
© NXP B.V. 2011. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 4 — 4 November 2011
2 of 15
NXP Semiconductors
74LVC38A
Quad 2-input NAND gate; open-drain
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
L
H
H
[1]
Function selection
[1]
Output
nB
L
H
L
H
nY
Z
Z
Z
L
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0
[1]
Min
0.5
50
0.5
50
[2]
[2]
Max
+6.5
-
+6.5
-
+6.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
< 0
active mode
high-impedance mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
74LVC38A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 4 November 2011
3 of 15
NXP Semiconductors
74LVC38A
Quad 2-input NAND gate; open-drain
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
active mode
high-impedance mode
in free air
input transition rise and fall V
CC
= 1.65 V to 2.7 V
rate
V
CC
= 2.7 V to 3.6 V
Conditions
Min
1.65
1.2
0
0
0
40
0
0
Typ
-
-
-
-
-
-
-
-
Max
5.5
-
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input V
CC
= 1.2 V
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OZ
I
OFF
input leakage
current
OFF-state
output current
power-off
leakage current
V
I
= 5.5 V or GND;
V
CC
= 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.20
0.45
0.6
0.4
0.55
0.55
5
5
10
-
-
-
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
0.8
20
20
20
V
V
V
V
V
V
A
A
A
1.08
1.7
2.0
0.7
V
CC
-
-
-
-
-
40 C
to +85
C
Min
Typ
[1]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.12
0.7
0.8
Max
40 C
to +125
C
Min
1.08
1.7
2.0
0.7
V
CC
-
-
-
-
-
-
-
0.12
0.7
0.8
0.65
V
CC
-
Max
V
V
V
V
V
V
V
V
Unit
0.65
V
CC
-
0.35
V
CC
-
0.35
V
CC
V
0.30
V
CC
-
0.30
V
CC
V
V
I
= V
IH
; V
O
= 5.5 V or GND; -
V
CC
= 1.65 V to 5.5 V
V
I
or V
O
= 5.5 V; V
CC
= 0 V
-
74LVC38A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 4 November 2011
4 of 15
NXP Semiconductors
74LVC38A
Quad 2-input NAND gate; open-drain
Table 6.
Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
I
CC
I
CC
supply current
additional
supply current
input
capacitance
Conditions
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input pin;
V
I
= V
CC
0.6 V; I
O
= 0 A;
V
CC
= 2.7 V to 5.5 V
V
CC
= 0 V to 5.5 V;
V
I
= GND to V
CC
-
-
40 C
to +85
C
Min
Typ
[1]
0.1
5
10
500
Max
-
-
40 C
to +125
C
Min
40
5000
Max
A
A
Unit
C
I
-
4.0
-
-
-
pF
[1]
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see
Figure 7.
Symbol Parameter
t
PZL
OFF-state to LOW
propagation delay
Conditions
nA, nB to nY; see
Figure 6
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
t
PLZ
LOW to OFF-state
propagation delay
nA, nB to nY; see
Figure 6
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
t
sk(o)
output skew time
[2]
40 C
to +85
C
Min
-
1.0
0.5
0.5
0.5
-
1.0
0.5
1.0
1.0
-
Typ
[1]
5.7
2.6
1.8
1.7
1.8
5.7
2.7
1.5
2.6
2.3
-
Max
-
6.0
3.3
2.9
3.0
-
6.0
3.3
3.8
3.6
1.0
40 C
to +125
C
Unit
Min
-
1.0
0.5
0.5
0.5
-
1.0
0.5
1.0
1.0
-
Max
-
6.9
3.8
4.0
4.0
-
6.9
3.8
5.0
4.5
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
74LVC38A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 4 November 2011
5 of 15
