74LVT2240 • 74LVTH2240 Low Voltage Inverting Octal Buffer/Line Driver with 3-STATE Outputs and 25: Series
Resistors in the Outputs
July 1999
Revised March 2005
74LVT2240 • 74LVTH2240
Low Voltage Inverting Octal Buffer/Line Driver
with 3-STATE Outputs
and 25: Series Resistors in the Outputs
General Description
The LVT2240 and LVTH2240 are inverting octal buffers
and line drivers designed to be employed as memory
address drivers, clock drivers and bus oriented transmitters
or receivers which provides improved PC board density.
The equivalent 25
:
Series resistors helps reduce output
overshoot and undershoot.
The LVTH2240 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These inverting octal buffers and line drivers are designed
for low-voltage (3.3V) V
CC
applications, but with the capa-
bility to provide a TTL interface to a 5V environment. The
LVT2240 and LVTH2240 are fabricated with an advanced
BiCMOS technology to achieve high speed operation simi-
lar to 5V ABT while maintaining low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Equivalent 25
:
Series resistors on outputs
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH2240),
also available without bushold feature (74LVT2240)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
12 mA/
12 mA
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Order Number
74LVT2240WM
74LVT2240SJ
74LVT2240MTC
74LVTH2240WM
74LVTH2240SJ
74LVTH2240MTCX
(Note 1)
Package Number
M20B
M20D
MTC20
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
Available only in Tape and Reel.
© 2005 Fairchild Semiconductor Corporation
DS500212
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74LVT2240 • 74LVTH2240
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
Truth Tables
Inputs
OE
1
L
L
H
Inputs
I
n
L
H
X
H
L
Z
Outputs
(Pins 3, 5, 7, 9)
I
n
L
H
X
H
L
Z
Outputs
(Pins 12, 14, 16, 18)
Connection Diagram
OE
2
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
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2
74LVT2240 • 74LVTH2240
Absolute Maximum Ratings
(Note 2)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 3)
V
I
GND
V
O
GND
V
O
!
V
CC
Output at HIGH State
V
O
!
V
CC
Output at LOW State
V
V
mA
mA
mA
mA
mA
0.5 to
4.6
0.5 to
7.0
0.5 to
7.0
0.5 to
7.0
50
50
64
128
r
64
r
128
65 to
150
q
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH-Level Output Current
LOW-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
12
12
40
0
85
10
q
C
ns/V
'
t/
'
V
Note 2:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
3.0
V
OL
I
I(HOLD)
(Note 5)
I
I(OD)
(Note 5)
I
I
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
I
CCH
I
CCL
I
CCZ
Power Off Leakage Current
Power up/down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
3.0
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
Output LOW Voltage
Bushold Input Minimum Drive
2.7
3.0
3.0
75
V
CC
0.2
2.0
0.2
0.8
2.0
0.8
T
A
40
q
C to
85
q
C
Min
Typ
(Note 4)
Units
Max
Conditions
V
IK
V
IH
V
IL
V
OH
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
1.2
V
V
V
V
V
V
I
I
18 mA
V
O
t
V
CC
0.1V
V
O
d
0.1V or
I
OH
I
OH
I
OL
I
OL
V
I
V
I
100
P
A
12 mA
100
P
A
12 mA
0.8V
2.0V
P
A
P
A
P
A
P
A
10
75
500
(Note 6)
(Note 7)
V
I
V
I
V
I
V
I
V
O
V
I
V
O
V
O
5.5V
0V or V
CC
0V
V
CC
0.5V to 3.0V
GND or V
CC
0.5V
3.0V
500
r
1
5
1
P
A
P
A
P
A
P
A
P
A
P
A
P
A
P
A
P
A
mA
mA
mA
r
100
r
100
5
5
10
0.19
5
0.19
0V
d
V
I
or V
O
d
5.5V
V
CC
V
O
d
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
3
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74LVT2240 • 74LVTH2240
DC Electrical Characteristics
Symbol
I
CCZ
Parameter
Power Supply Current
Increase in Power Supply Current
(Note 8)
Note 4:
All typical values are at V
CC
3.3V, T
A
25
q
C.
Note 5:
Applies to bushold versions only (74LVTH2240).
(Continued)
T
A
40
q
C to
85
q
C
Min
Typ
(Note 4)
Max
0.19
0.2
Units
mA
mA
Conditions
V
CC
d
V
O
d
5.5V,
Outputs Disabled
One Input at V
CC
0.6V
Other Inputs at V
CC
or GND
V
CC
(V)
3.6
3.6
'
I
CC
Note 6:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8:
This is the increase in supply current for each, input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
(Note 9)
T
A
Min
25
q
C
Typ
0.8
Max
V
V
Units
Conditions
C
L
50 pF, R
L
(Note 10)
500
:
0.8
Note 9:
Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 10:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
C
L
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output to Output Skew
(Note 12)
3.3V, T
A
25
q
C.
40
q
C to
85
q
C
50 pF, R
L
500
:
V
CC
Max
4.0
4.1
5.0
5.0
4.8
4.5
1.0
Min
1.0
1.0
1.0
1.1
1.9
1.8
2.7V
Max
4.8
4.4
6.0
5.6
5.5
4.5
1.0
Units
V
CC
3.3V
r
0.3V
Typ
(Note 11)
Propagation Delay Data to Output
Output Enable Time
Output Disable Time
1.0
1.0
1.0
1.1
1.9
1.8
ns
ns
ns
ns
Note 11:
All typical values are at V
CC
Note 12:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
Symbol
C
IN
C
OUT
(Note 13)
Parameter
Conditions
V
CC
V
CC
0V, V
I
0V or V
CC
0V or V
CC
3.0V, V
O
Typical
3
6
Units
pF
pF
Input Capacitance
Output Capacitance
Note 13:
Capacitance is measured at frequency f
1 MHz, per MIL-STD-883B, Method 3012.
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4
74LVT2240 • 74LVTH2240
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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