The 8T49N286 has one fractional-feedback PLL that can be used as a frequency translator with jitter attenuation or a frequency synthesizer. It is equipped with six integer and two fractional output dividers, allowing the generation of up to eight different output frequencies, ranging from 8 kHz to 1 GHz. Output frequencies can be completely independent of the input frequencies, and up to four of these frequencies can be completely independent of each other. The eight outputs may select among LVPECL, LVDS, H
Samacsys Manufacturer
Renesas Electronics
Samacsys Modified On
2023-10-24 19:30:29
YTEOL
6.98
JESD-30 代码
S-XQCC-N72
JESD-609代码
e3
长度
10 mm
湿度敏感等级
3
端子数量
72
最高工作温度
85 °C
最低工作温度
-40 °C
最大输出时钟频率
1000 MHz
封装主体材料
UNSPECIFIED
封装代码
HVQCCN
封装等效代码
LCC72,.39SQ,20
封装形状
SQUARE
封装形式
CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）
260
主时钟/晶体标称频率
40 MHz
座面最大高度
1 mm
最大压摆率
275 mA
最大供电电压
2.625 V
最小供电电压
2.375 V
标称供电电压
2.5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
TIN
端子形式
NO LEAD
端子节距
0.5 mm
端子位置
QUAD
宽度
10 mm
uPs/uCs/外围集成电路类型
CLOCK GENERATOR, PROCESSOR SPECIFIC
文档预览
FemtoClock
®
NG Octal Universal
Frequency Translator
8T49N286
Datasheet
Description
The 8T49N286 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to eight different output frequencies, ranging
from 8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS,
HCSL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N286 accepts up to four differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. The
other two input clocks are intended for redundant backup of the
primary clocks and must be related in frequency to their primary.
The device supports hitless reference switching between input
clocks. The device monitors all input clocks for Loss of Signal (LOS),
and generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or ungapped
clocks.
The 8T49N286 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
Each PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I
2
C interface. It also supports
I
2
C master capability to allow the register configuration to be read
from an external EEPROM. The user may select whether the
programming interface uses I
2
C protocols or SPI protocols, however
in SPI mode, read from the external EEPROM is not supported.
•
•
•
•
•
•
•
•
•
SyncE (G.8262) applications
Wireless base station baseband
Data communications
100G Ethernet
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS Typical Jitter (including spurs), 12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts up to four LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
•
Accepts frequencies ranging from 8kHz up to 875MHz
•
Auto and manual input clock selection with hitless switching
•
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
