INTEGRATED CIRCUITS
DATA SHEET
TDA6402; TDA6402A; TDA6403;
TDA6403A
5 V mixers/oscillators and
synthesizers for cable TV and VCR
2-band tuners
Product specification
Supersedes data of 1998 Jul 28
File under Integrated Circuits, IC02
2000 Jan 24
Philips Semiconductors
Product specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
FEATURES
•
Single-chip 5 V mixer/oscillator and synthesizer for
cable TV and VCR tuners
•
Synthesizer function compatible with existing TSA5526
•
Universal bus protocol (I
2
C-bus or 3-wire bus)
– Bus protocol for 18 or 19-bit transmission (3-wire
bus)
– Extra protocol for 27-bit transmission (test modes and
features for 3-wire bus)
– Address + 4 data bytes transmission (I
2
C-bus ‘write’
mode)
– Address + 1 status byte (I
2
C-bus ‘read’ mode)
– 4 independent I
2
C-bus addresses.
•
1 PNP buffer for UHF band selection (25 mA)
•
3 PNP buffers for general purpose, e.g. 2 VHF
sub-bands, FM sound trap (25 mA)
•
33 V tuning voltage output
•
In-lock detector
•
5-step A/D converter (3 bits in I
2
C-bus mode)
•
15-bit programmable divider
•
Programmable reference divider ratio (512, 640 or
1024)
•
Programmable charge pump current (60 or 280
µA)
•
Programmable automatic charge pump current switch
•
Varicap drive disable
•
Mixer/oscillator function compatible with existing
TDA5732
•
Balanced mixer with a common emitter input for VHF
(single input)
•
Balanced mixer with a common base input for UHF
(balanced input)
•
2-pin common emitter oscillator for VHF
•
4-pin common emitter oscillator for UHF
•
IF preamplifier with asymmetrical 75
Ω
output
impedance to drive a low-ohmic impedance (75
Ω)
•
Low power
•
Low radiation
•
Small size
•
The TDA6402A and TDA6403A differ from the TDA6402
and TDA6403 by the UHF port protocol in the I
2
C-bus
mode (see Tables 3 and 4).
APPLICATIONS
TDA6402; TDA6402A;
TDA6403; TDA6403A
•
Cable tuners for TV and VCR (switched concept for
VHF)
•
Recommended RF bands for the USA:
55.25 to 133.25 MHz, 139.25 to 361.25 MHz and
367.25 to 801.25 MHz.
GENERAL DESCRIPTION
The TDA6402, TDA6402A, TDA6403 and TDA6403A are
programmable 2-band mixers/oscillators and synthesizers
intended for VHF/UHF cable tuners (see Fig.1).
The devices include two double balanced mixers and two
oscillators for the VHF and UHF band respectively, an IF
amplifier and a PLL synthesizer. The VHF band can be
split-up into two sub-bands using a proper oscillator
application and a switchable inductor. Two pins are
available between the mixer output and the IF amplifier
input to enable IF filtering for improved signal handling.
Four PNP ports are provided. Band selection is provided
by using pin PUHF. When PUHF is ‘ON’, the UHF
mixer-oscillator is active and the VHF band is switched off.
When PUHF is ‘OFF’, the VHF mixer-oscillator is active
and the UHF band is ‘OFF’. PVHFL and PVHFH are used
to select the VHF sub-bands. FMST is a general purpose
port, that can be used to switch an FM sound trap. When
it is used, the sum of the collector currents has to be limited
to 30 mA.
The synthesizer consists of a divide-by-eight prescaler, a
15-bit programmable divider, a crystal oscillator and its
programmable reference divider and a phase/frequency
detector combined with a charge pump which drives the
tuning amplifier, including 33 V output (V33) at pin VT.
Depending on the reference divider ratio (512, 640 or
1024), the phase comparator operates at 7.8125 kHz,
6.25 kHz or 3.90625 kHz with a 4 MHz crystal.
2000 Jan 24
2
Philips Semiconductors
Product specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
The device can be controlled according to the I
2
C-bus
format or 3-wire bus format depending on the voltage
applied to pin SW (see Table 2). In the 3-wire bus mode
(SW = HIGH), pin LOCK/ADC is the LOCK output.
The LOCK output is LOW when the PLL loop is locked.
In the I
2
C-bus mode (SW = LOW), the lock detector bit FL
is set to logic 1 when the loop is locked and is read on the
SDA line (Status Byte; SB) during a READ operation in
I
2
C-bus mode only. The Analog-to-Digital Converter
(ADC) input is available on pin LOCK/ADC for digital AFC
control in the I
2
C-bus mode only. The ADC code is read
during a READ operation on the I
2
C-bus (see Table 11).
In test mode, pin LOCK/ADC is used as a TEST output for
f
REF
and
1
⁄
2
f
DIV
, in both I
2
C-bus mode and 3-wire bus mode
(see Table 7).
When the automatic charge pump current switch mode is
activated and when the loop is phase-locked, the charge
pump current value is automatically switched to LOW. This
action is taken to improve the carrier-to-noise ratio.
The status of this feature can be read in the ACPS flag
during a READ operation on the I
2
C-bus (see Table 9).
Table 1
Data word length for 3-wire bus
TYPE NUMBER
TDA6402; TDA6402A; TDA6403; TDA6403A
TDA6402; TDA6402A; TDA6403; TDA6403A
TDA6402; TDA6402A; TDA6403; TDA6403A
Note
DATA WORD
18-bit
19-bit
27-bit
TDA6402; TDA6402A;
TDA6403; TDA6403A
I
2
C-bus mode (SW = GND)
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four ports, set the charge pump current and set the
reference divider ratio. The device has four independent
I
2
C-bus addresses which can be selected by applying a
specific voltage on input CE (see Table 6).
3-wire bus mode (SW = OPEN or VCC)
Data is transmitted to the devices during a HIGH-level on
input CE (enable line). The device is compatible with 18-bit
and 19-bit data formats, as shown in Figs 4 and 5. The first
four bits are used to program the PNP ports and the
remaining bits control the programmable divider. A 27-bit
data format may also be used to set the charge pump
current, the reference divider ratio and for test purposes
(see Fig.6).
It is not allowed to address the devices with words whose
length is different from 18, 19 or 27 bits.
REFERENCE DIVIDER
(1)
512
1024
programmable
FREQUENCY STEP
62.50 kHz
31.25 kHz
programmable
1. The selection of the reference divider is given by an automatic identification of the data word length. When the 27-bit
format is used, the reference divider is controlled by RSA and RSB bits (see Table 8). More details are given in
Chapter “PLL functional description”, Section “3-wire bus mode (SW = OPEN or V
CC
)”.
2000 Jan 24
3
Philips Semiconductors
Product specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
QUICK REFERENCE DATA
Measured over full voltage and temperature ranges; unless otherwise specified.
SYMBOL
V
CC
I
CC
f
XTAL
I
o(PNP)
P
tot
T
stg
T
amb
f
RF
G
V
NF
V
o
PARAMETER
supply voltage
supply current
crystal oscillator input frequency
PNP port output current
total power dissipation
IC storage temperature
ambient temperature
RF frequency
voltage gain
noise figure
output voltage causing 1% cross
modulation in channel
VHF band
UHF band
VHF band
UHF band
VHF band
UHF band
VHF band
UHF band
note 1
note 2
CONDITIONS
operating
all PNP ports are ‘OFF’
−
TDA6402; TDA6402A;
TDA6403; TDA6403A
MIN.
4.5
3.2
−
−
−40
−20
55.25
367.25
−
−
−
−
−
−
5
TYP.
71
4.0
−
−
−
−
−
−
19
29
8.5
9
108
108
−
MAX.
5.5
4.48
30
490
+150
+85
361.25
801.25
−
−
−
−
−
−
UNIT
V
mA
MHz
mA
mW
°C
°C
MHz
MHz
dB
dB
dB
dB
dBµV
dBµV
Notes
1. One buffer ‘ON’, I
o
= 25 mA; two buffers ‘ON’, maximum sum of I
o
= 30 mA.
1 V33
-
--
2
=
V
CC
× (
I
CC
–
I
o
)
+
V
CE(sat PNP)
×
I
o
+
----------------------
-
22 kΩ
2
2. The power dissipation is calculated as follows: P
tot
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA6402M;
TDA6402AM
TDA6403M;
TDA6403AM
SSOP28
SSOP28
DESCRIPTION
plastic shrink small outline package; 28 leads; body width 5.3 mm
plastic shrink small outline package; 28 leads; body width 5.3 mm
VERSION
SOT341-1
SOT341-1
2000 Jan 24
4
Philips Semiconductors
Product specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
BLOCK DIAGRAM
TDA6402; TDA6402A;
TDA6403; TDA6403A
handbook, full pagewidth
IFFIL1 IFFIL2
5 (24) 6 (23)
VCC
19 (10)
(5) 24
VHFOSCOC
VHFIN
3 (26)
RF INPUT
VHF
BS
BS
VHF
MIXER
BS
(6) 23
IF
PREAMPLIFIER
(9) 20
VHF
OSCILLATOR
(7) 22
VHFOSCIB
OSCGND
IFOUT
RFGND
4 (25)
TDA6402
TDA6402A
TDA6403
TDA6403A
RF INPUT
UHF
BS
BS
(1) 28
UHFIN1
UHFIN2
1 (28)
2 (27)
UHF
MIXER
BS
UHF
OSCILLATOR
(2) 27
(3) 26
(4) 25
UHFOSCIB2
UHFOSCOC2
UHFOSCOC1
UHFOSCIB1
(13) 16
XTAL
18 (11)
XTAL
OSCILLATOR
4 MHz
PRESCALER
DIVIDE BY
512, 640, 1024
RSA
PRESCALER
DIVIDE BY 8
RSB
fREF
PHASE
COMPARATOR
fDIV
T0, T1, T2 CP
IN LOCK
DETECTOR
POWER-DOWN
DETECTOR
FL
14 (15)
13 (16)
11 (18)
15-BIT
FREQUENCY
REGISTER
CHARGE
PUMP
(12) 17
OPAMP
CP
VT
15-BIT
PROGRAMMABLE
DIVIDER
OS
FL
CONTROL
REGISTER
CL
DA
SW
SCL
SDA
I
2
C / 3-WIRE BUS TRANSCEIVER
FL
fREF
1/2fDIV
UHF
3-BIT A/D
CONVERTER
GATE
BS
T0, T1, T2
15 (14)
LOCK/ADC
PUHF
9 (20)
8 (21)
7 (22)
10 (19)
MGE692
CP
T2
T1
T0 RSA RSB OS
SW CE/AS
PORT
REGISTER
VHFH VHFL FMST
(8) 21
CE/AS
12 (17)
GND
PVHFH
PVHFL
FMST
The pin numbers in parenthesis represent the TDA6403 and TDA6403A.
Fig.1 Block diagram.
2000 Jan 24
5
