74AVC16374-Q100
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Rev. 1 — 16 September 2013
Product data sheet
1. General description
The 74AVC16374-Q100 is a 16-bit edge triggered flip-flop featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus-oriented applications. The
74AVC16374-Q100 consist of 2 sections of 8 edge-triggered flip-flops. A clock input (CP)
and an output enable (OE) are provided per 8-bit section.
The 74AVC16374-Q100 is designed to have an extremely fast propagation delay and a
minimum amount of power consumption.
To ensure the high-impedance output state during power-up or power-down, nOE should
be tied to VCC through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line
drive during transient (see
Figure 5
and
Figure 6).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from
40 C
to +85
C
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-1A (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
CMOS low power consumption
Input/output tolerant up to 3.6 V
Dynamic Controlled Output (DCO) circuit dynamically changes output impedance,
resulting in noise reduction without speed degradation
Low inductance multiple V
CC
and GND pins to minimize noise and ground bounce
Supports Live Insertion
NXP Semiconductors
74AVC16374-Q100
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AVC16374DGG-Q100
40 C
to +85
C
TSSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT362-1
Type number
4. Functional diagram
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
mna577
1OE
1CP
2OE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1EN
C1
2EN
C2
1D
1
2
3
5
6
8
9
11
12
2D
2
13
14
16
17
19
20
22
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
1OE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1CP
48
24
2OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2CP
25
mna576
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
Fig 1.
IEC logic symbol
Fig 2.
Logic symbol
74AVC16374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
2 of 16
NXP Semiconductors
74AVC16374-Q100
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
1D0
D
CP
Q
1Q0
1CP
FF1
1OE
to 7 other channels
2D0
D
CP
Q
2Q0
2CP
FF9
2OE
to 7 other channels
mna578
Fig 3.
Logic diagram
74AVC16374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
3 of 16
NXP Semiconductors
74AVC16374-Q100
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
1OE
1Q0 to 1Q7
GND
V
CC
2Q0 to 2Q7
2OE
2CP
2D0 to 2D7
1D0 to 1D7
1CP
Pin description
Pin
1
2, 3, 5, 6, 8, 9, 11, 12
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
13, 14, 16, 17, 19, 20, 22, 23
24
25
36, 35, 33, 32, 30, 29, 27, 26
47, 46, 44, 43, 41, 40, 38, 37
48
Description
output enable input (active LOW)
3-state flip-flop outputs
ground (0 V)
supply voltage
3-state flip-flop outputs
output enable input (active LOW)
clock input
data input/output
data input/output
clock input
74AVC16374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
4 of 16
NXP Semiconductors
74AVC16374-Q100
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
6. Functional description
Table 3.
Function table
[1]
Inputs
nOE
Load and read register
Load register and disable outputs
L
L
H
H
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high-impedance OFF-state
= LOW-to-HIGH CP transition
Operating modes
Internal flip-flops
nCp
nDn
I
h
I
h
L
H
L
H
Outputs
nQn
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
0.5
50
[1]
[1]
Max
+4.6
50
+4.6
-
V
CC
+ 0.5
+4.6
50
+100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
< 0 V
output HIGH or LOW
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +85
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Above 60
C,
the value of P
tot
derates linearly with 5.5 mW/K.
74AVC16374_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
5 of 16
