Freescale Semiconductor
Technical Data
Document Number:MPC8309EC
Rev 4, 12/2014
MPC8309
PowerQUICC II Pro Integrated
Communications Processor
Family Hardware Specifications
This document provides an overview of the
MPC8309
PowerQUICC II Pro
processor features. The MPC8309 is a
cost-effective, highly integrated communications processor
that addresses the requirements of several networking
applications, including residential gateways,
modem/routers, industrial control, and test and measurement
applications. The MPC8309 extends current PowerQUICC
offerings, adding higher CPU performance, additional
functionality, and faster interfaces, while addressing the
requirements related to time-to-market, price, power
consumption, and board real estate. This document describes
the electrical characteristics of MPC8309.
To locate published errata or updates for this document, refer
to the MPC8309 product summary page on our website
listed on the back cover of this document or contact your
local Freescale sales office.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ethernet and MII Management . . . . . . . . . . . . . . . . . 22
TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
eSDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 52
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
System Design Information . . . . . . . . . . . . . . . . . . . 75
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 78
Document Revision History . . . . . . . . . . . . . . . . . . . 80
© 2011, 2014 Freescale Semiconductor, Inc. All rights reserved.
Overview
1
Overview
The MPC8309 incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology,
which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory
management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and
a 16/32-bit DDR2 memory controller with 8-bit ECC.
A new communications complex based on QUICC Engine technology forms the heart of the networking
capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit
RISC controller. Protocol support is provided by the main workhorses of the device—the unified
communication controllers (UCCs). A block diagram of the MPC8309 is shown in the following figure.
2x DUART
I2C
Timers
GPIO
SPI
RTC
e300c3 Core with Power
Management
16-KB
I-Cache
Interrupt
Controller
FPU
16-KB
D-Cache
ULPI
USB 2.0 HS
Host/Device/OTG
Enhanced
Local Bus
DDR2
Controller
QUICC Engine™ Block
Accelerators
Baud Rate
Generators
16 KB Multi-User RAM
48 KB Instruction RAM
Single 32-bit RISC CP Serial DMA
UCC1
UCC2
UCC3
UCC5
UCC7
4 FlexCAN
IO
Sequencer
eSDHC
DMA
Engine 2
DMA
Engine 1
PCI Controller
Time Slot Assigner
Serial Interface
2x TDM Ports
2x HDLC
2 RMII/MII
1 RMII/MII
2x IEEE 1588
Figure 1. MPC8309 Block Diagram
Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII
Ethernet, HDLC and TDM.
In summary, the MPC8309 provides users with a highly integrated, fully programmable communications
processor. This helps to ensure that a low-cost system solution can be quickly developed and offers
flexibility to accommodate new standards and evolving system requirements.
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
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Freescale Semiconductor
Overview
1.1
Features
The major features of the device are as follows:
• e300c3 Power Architecture processor core
— Enhanced version of the MPC603e core
— High-performance, superscalar processor core with a four-stage pipeline and low interrupt
latency times
— Floating-point, dual integer units, load/store, system register, and branch processing units
— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities
— Dynamic power management
— Enhanced hardware program debug features
— Software-compatible with Freescale processor families implementing Power Architecture
technology
— Separate PLL that is clocked by the system bus clock
— Performance monitor
• QUICC Engine block
— 32-bit RISC controller for flexible support of the communications peripherals with the
following features:
– One clock per instruction
– Separate PLL for operating frequency that is independent of system’s bus and e300 core
frequency for power and performance optimization
– 32-bit instruction object code
– Executes code from internal IRAM
– 32-bit arithmetic logic unit (ALU) data path
– Modular architecture allowing for easy functional enhancements
– Slave bus for CPU access of registers and multiuser RAM space
– 48 Kbytes of instruction RAM
– 16 Kbytes of multiuser data RAM
– Serial DMA channel for receive and transmit on all serial channels
— Five unified communication controllers (UCCs) supporting the following protocols and
interfaces:
– 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.
– IEEE Std. 1588™ support
– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)
– HDLC Bus (bit rate up to 10 Mbps)
– Asynchronous HDLC (bit rate up to 2 Mbps)
– Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each
running at 64 kbps
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
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Overview
•
•
•
For more information on QUICC Engine sub-modules, see
QUICC Engine Block Reference
Manual with Protocol Interworking.
DDR SDRAM memory controller
— Programmable timing supporting DDR2 SDRAM
— Integrated SDRAM clock generation
— Supports 8-bit ECC
— 16/32-bit data interface, up to 333-MHz data rate
— 14 address lines
— The following SDRAM configurations are supported:
– Up to two physical banks (chip selects), 512-Mbyte addressable space for 32 bit data
interface
– 64-Mbit to 2-Gbit devices with x8/x16/x32 data ports (no direct x4 support)
— One 16-bit device or two 8-bit devices on a 16-bit bus, or two 16-bit devices or four 8-bit
devices on a 32-bit bus Support for up to 16 simultaneous open pages for DDR2
— Two clock pair to support up to 4 DRAM devices
— Supports auto refresh
— On-the-fly power management using CKE
Enhanced local bus controller (eLBC)
— Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz
— Eight chip selects supporting eight external slaves
– Four chip selects dedicated
– Four chip selects offered as multiplexed option
— Supports boot from parallel NOR Flash and parallel NAND Flash
— Supports programmable clock ratio dividers
— Up to eight-beat burst transfers
— 16- and 8-bit ports, separate LWE for each 8 bit
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– NAND Flash control machine (FCM)
— Variable memory block sizes for FCM, GPCM, and UPM mode
— Default boot ROM chip select with configurable bus width (8 or 16)
— Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC
slave devices
Integrated programmable interrupt controller (IPIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for external and internal discrete interrupt sources
— Programmable highest priority request
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
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Freescale Semiconductor
Overview
•
•
— Six groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Unique vector number for each interrupt source
PCI interface
— Designed to comply with
PCI Local Bus Specification, Revision 2.3
— 32-bit PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— Not 5-V compatible
— Support for host and agent modes
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting three masters on PCI
— Arbiter support for two-level priority request/grant signal pairs
— Support for accesses to all PCI address spaces
— Support for parity
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Mapping from an external 32-/64-bit address space to the internal 32-bit local space
— Support for dual address cycle (DAC) (as a target only)
— Internal configuration registers accessible from PCI
— Selectable snooping for inbound transactions
— Four outbound Translation Address Windows
– Support for mapping 32-bit internal local memory space to an external 32-bit PCI address
space and translating that address within the PCI space
— Four inbound Translation Address Windows corresponding to defined PCI BARs
– The first BAR is 32-bits and dedicated to on-chip register access
– The second BAR is 32-bits for general use
– The remaining two BARs may be 32- or 64-bits and are also for general use
Enhanced secure digital host controller (eSDHC)
— Compatible with the
SD Host Controller Standard Specification Version 2.0
with test event
register support
— Compatible with the
MMC System Specification Version 4.2
— Compatible with the
SD Memory Card Specification Version 2.0
and supports the high capacity
SD memory card
— Compatible with the
SD Input/Output (SDIO) Card Specification, Version 2.0
— Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,
MMCplus, and RS-MMC cards
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
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