DATASHEET
Six Output Differential Buffer for PCIe Gen 2
Description
The
9DB106
zero-delay buffer supports PCIe Gen1 and Gen2
clocking requirements. The
9DB106
is driven by a differential SRC
output pair from an IDT CK410/CK505-compliant main clock
generator. It attenuates jitter on the input clock and has a selectable
PLL bandwidth to maximize performance in systems with or without
Spread-Spectrum clocking. An SMBus interface allows control of
the PLL bandwidth and bypass options, while 2 clock request
(CLKREQ#) pins make the
9DB106
suitable for Express Card
applications.
9DB106
Features/Benefits
•
•
•
•
•
CLKREQ# pin for outputs 1 and 4/ supports Express Card
applications
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible/tracks spreading input clock
for low EMI
SMBus Interface/unused outputs can be disabled
Recommended Applications
6 Output Differential Buffer for PCIe Gen 2
Key Specifications
•
•
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
Output Features
•
6 - 0.7V current mode differential output pairs (HCSL)
Functional Block Diagram
CLKREQ1#
CLKREQ4#
PCIEX1
CLK_INT
SPREAD
COMPATIBLE
PLL
PCIEX4
C LK_INC
PLL_BW
SMBDAT
SMBCLK
CONTROL
LOGIC
PCIEX(0,2,3,5)
IREF
IDT
®
Six Output Differential Buffer for PCIe Gen 2
9DB106
REV L 05/24/12
1
9DB106
Six Output Differential Buffer for PCIe Gen 2
Pin Configuration
PLL_BW
CLK_INT
CLK_INC
vCLKREQ1#
PCIEXT0
PCIEXC0
VDD
GND
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
VDD
SMBDAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
vCLKR EQ4#
PCIEXT5
PCIEXC5
VDD
GND
PCIEXT4
PCIEXC4
PCIEXT3
PCIEXC3
VDD
SMBCLK
Note:Pins
preceeded by ' v ' have internal
120K ohm pull down resistors
28-pin SSOP & TSSOP
Power Groups
Pin Number
VDD
GND
7, 13, 16, 22
8,21
TBD
TBD
N/A
27
28
27
Description
PCI Express Outputs
SMBUS
IREF
Analog VDD & GND for PLL core
IDT
®
Six Output Differential Buffer for PCIe Gen 2
9DB106
9DB106
REV L 05/24/12
2
9DB106
Six Output Differential Buffer for PCIe Gen 2
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN NAME
PLL_BW
CLK_INT
CLK_INC
vCLKREQ1#
PCIEXT0
PCIEXC0
VDD
GND
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
VDD
SMBDAT
SMBCLK
VDD
PCIEXC3
PCIEXT3
PCIEXC4
PCIEXT4
GND
VDD
PCIEXC5
PCIEXT5
vCLKREQ4#
PIN TYPE
IN
IN
IN
IN
OUT
OUT
PWR
IN
OUT
OUT
OUT
OUT
PWR
I/O
IN
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = low, 1= high
True Input for differential reference clock.
Complementary Input for differential reference clock.
Output enable for PCI Express output pair 1.
0 = enabled, 1 =disabled
True clock of differential PCI_Express pair.
Complementary clock of differential PCI_Express pair.
Power supply, nominal 3.3V
Ground pin.
True clock of differential PCI_Express pair.
Complementary clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complementary clock of differential PCI_Express pair.
Power supply, nominal 3.3V
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
Complementary clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complementary clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Ground pin.
Power supply, nominal 3.3V
Complementary clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Output enable for PCI Express output pair 4.
0 = enabled, 1 =disabled
This pin establishes the reference for the differential current-mode
output pairs. It requires a fixed precision resistor to ground.
475ohm is the standard value for 100ohm differential impedance.
Other impedances require different values. See data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
IDT
®
Six Output Differential Buffer for PCIe Gen 2
9DB106
REV L 05/24/12
3
9DB106
Six Output Differential Buffer for PCIe Gen 2
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDA
VDD
V
IL
V
IH
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
MIN
TYP
MAX
4.6
4.6
V
DD
+0.5V
5.5V
UNITS
V
V
V
V
V
C
°
C
V
°
NOTES
1,2
1,2
1
1
1
1
1
1
GND-0.5
Except for SMBus interface
SMBus clock and data pins
-65
Human Body Model
2000
150
125
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
T
COM
T
IND
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Operating Supply Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Input Spread Spectrum
Modulation Frequency
OE# Latency
SMBus Voltage
Low-level Output Voltage
Current sinking at
V
OL
= 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
1
2
3
CONDITIONS
Commmercial range
Industrial range
3.3 V +/-5%
3.3 V +/-5%
V
IN
= V
DD
V
IN
= 0 V; Inputs with no pull-
up resistors
V
IN
= 0 V; Inputs with pull-up
resistors
Full Active, C
L
= Full load;
all differential pairs tri-stated
V
DD
= 3.3 V
Logic Inputs
Output pin capacitance
From VDD reaching 3.1V and
input clock stable
Triangular Modulation
MIN
0
-40
2
V
SS
- 0.3
-5
-5
-200
TYP
MAX
70
85
V
DD
+ 0.3
0.8
5
UNITS Notes
°
C
°
C
V
V
uA
uA
uA
1
1
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
1
1
1,3
1
1
1
1
1
I
DD3.3OP
F
i
L
pin
C
IN
C
OUT
T
STAB
130
30
80
100
150
40
105
7
5
4.5
1.8
mA
mA
MHz
nH
pF
pF
ms
kHz
cycles
V
V
mA
30
1
2.7
33
3
5.5
0.4
t
LATOE#
V
DD
V
OL
I
PULLUP
T
RI2C
T
FI2C
DIF start after OE# assertion
DIF stop after OE#
deassertion
@ I
PULLUP
4
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1000
300
ns
ns
Guaranteed by design and characterization, not 100% tested in production.
Except differential input clock
Time from deassertion until outputs are >200mV
9DB106
REV L 05/24/12
IDT
®
Six Output Differential Buffer for PCIe Gen 2
4
9DB106
Six Output Differential Buffer for PCIe Gen 2
Electrical Characteristics - Clock Input Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage -
DIF_IN
Input Low Voltage -
DIF_IN
Input Common Mode
Voltage - DIF_IN
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to
Cycle
1
SYMBOL
V
IHDIF
V
ILDIF
V
COM
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
CONDITIONS
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
Peak to Peak value
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential
wavefrom
Differential Measurement
MIN
600
V
SS
- 300
300
300
0.4
-5
45
0
TYP
800
0
MAX
1150
300
1000
1450
8
5
55
125
UNITS NOTES
mV
mV
mV
mV
V/ns
uA
%
ps
1
1
1
1
1,2
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics - PLL Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
Group
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Parameter
j
peak-hibw
j
peak-lobw
pll
HIBW
pll
LOBW
Description
(PLL_BW = 1)
(PLL_BW = 0)
(PLL_BW = 1)
(PLL_BW = 0)
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=1)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
Min
0
0
2
0.4
Typ
1
1
2.5
0.5
40
2.7
Max
2.5
2
3
1
108
3.1
Units
dB
dB
MHz
MHz
ps
ps rms
Notes
1,4
1,4
1,5
1,5
1,2,3
1,2,3
Jitter, Phase
t
jphasePLL
2.2
1.3
3.1
3
ps rms
ps rms
1,2,3
1,2,3
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
IDT
®
Six Output Differential Buffer for PCIe Gen 2
9DB106
REV L 05/24/12
5
