DATASHEET
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
9DB833
General Description
The 9DB833 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB833 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator.
Features/Benefits
•
3 Selectable SMBus Addresses; multiple devices can
•
•
•
•
•
•
share the same SMBus Segment
OE# pins; suitable for Express Card applications
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
SMBus Interface; unused outputs can be disabled
Supports undriven differential outputs in Power Down
mode for power management
Recommended Application
8 output PCIe Gen1,2,3 zero-delay/fanout buffer
Output Features
•
•
•
•
•
8 - 0.7V current-mode differential HCSL output pairs
Supports zero delay buffer mode and fanout mode
Selectable bandwidth
50-110 MHz operation in PLL mode
5-166 MHz operation in Bypass mode
Key Specifications
•
Outputs cycle-cycle jitter <50ps
•
Output to Output skew <50ps
•
Phase jitter: PCIe Gen3 <1.0ps rm
Block Diagram
8
OE(7:0)#
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
STOP
LOGIC
8
DIF(7:0))
PD#
BYP#_LOBW_HIBW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
LOCK
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
1
9DB833
REV H 06/07/16
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Pin Configuration
SRC_DIV#
VDDR
GND
SRC_IN
SRC_IN#
OE0#
OE3#
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE1#
OE2#
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYP#_HIBW_LOBW
SMBCLK
SMBDAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
LOCK
OE7#
OE4#
DIF_7
DIF_7#
PD#
VDD
DIF_6
DIF_6#
OE6#
OE5#
DIF_5
DIF_5#
GND
VDD
DIF_4
DIF_4#
SMB_ADR_tri
VDD
GND
GND
Notes:
Highlighted Pins are the differences between 9DB803 and 9DB833.
Pin 22 and Pin 28 are latched on power up. Please make sure that the
power supply to the pullup/pulldown resistors ramps at the same time
as the main supply to the chip.
Operating Mode Readback Table
BYP#_LOBW_HIBW
Low
Mid
High
MODE
Byte0, bit 3 Byte 0 bit 1
Bypass
0
0
PLL 100M Hi BW
1
0
PLL 100M Low BW
0
1
Power Connections
Pin Number
Description
VDD
GND
2
3
SRC_IN/SRC_IN#
11,19,31,39
10,18, 25,32
DIF(7:0)
27
26
DIGITAL VDD/GND
48
47
Analog VDD/GND for PLL in IREF
For best results, treat pin 2 as analog VDD.
9DB833
SMBus Address Selection and Readback
SMB_ADR_tri
Low
Mid
High
Address
DA/DB
DC/DD
D8/D9
Tri-level Input Logic Levels
State of Pin
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.0V
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
2
9DB833
REV H 06/07/16
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
SRC_DIV#
VDDR
GND
SRC_IN
SRC_IN#
OE0#
OE3#
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE1#
OE2#
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYP#_HIBW_LOBW
SMBCLK
SMBDAT
PIN TYPE
IN
PWR
PWR
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
I/O
DESCRIPTION
Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
3.3V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active low input for enabling DIF pair 0.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Tri-level input to select bypass mode, Hi BW PLL, or Lo BW PLL mode
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
3
9DB833
REV H 06/07/16
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Pin Descriptions (cont.)
PIN #
PIN NAME
25
GND
26
GND
27
VDD
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
SMB_ADR_tri
DIF_4#
DIF_4
VDD
GND
DIF_5#
DIF_5
OE5#
OE6#
DIF_6#
DIF_6
VDD
PD#
DIF_7#
DIF_7
OE4#
OE7#
LOCK
PIN TYPE
PWR
PWR
PWR
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
IN
OUT
OUT
IN
IN
OUT
DESCRIPTION
Ground pin.
Ground pin.
Power supply, nominal 3.3V
SMBus address select bit. This is a tri-level input that decodes 1 of 3 SMBus
Addresses.
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
3.3V output indicating PLL Lock Status. This pin goes high when lock is achieved.
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
46
47
48
IREF
GNDA
VDDA
OUT
PWR
PWR
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
4
9DB833
REV H 06/07/16
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DB833. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDA/R
VDD
V
IL
V
IH
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
MIN
TYP
MAX
4.6
4.6
V
DD
+0.5V
5.5V
UNITS NOTES
V
V
V
V
V
C
°C
V
°
GND-0.5
Except for SMBus interface
SMBus clock and data pins
-65
Human Body Model
2000
150
125
1,2
1,2
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics–DIF_IN Clock Input Parameters
T
AMB
=T
COM
or T
IND
unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Input Crossover Voltage -
DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
SYMBOL
V
CROSS
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
CONDITIONS
Cross Over Voltage
Differential value
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential wavefrom
Differential Measurement
MIN
150
300
1
-5
45
0
TYP
375
MAX
900
UNITS NOTES
mV
mV
1
1
1,2
1
1
8
5
55
125
V/ns
uA
%
ps
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics–Current Consumption
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Operating Supply Current
Powerdown Current
1
SYMBOL
I
DD3.3OP
I
DD3.3PD
I
DD3.3PDZ
CONDITIONS
All outputs active @100MHz, PLL Mode,
C
L
= Full load;
All diff pairs driven
All differential pairs tri-stated
MIN
TYP
164
53
3
MAX
200
60
6
UNITS
mA
mA
mA
NOTES
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
5
9DB833
REV H 06/07/16
