DATASHEET
Eight Output Differential Frequency Generator
for PCIe Gen3 and QPI
General Description:
The 9FG830 is a Frequency Timing Generator that provides 8
HCSL differential output pairs. These outputs support PCI-Express
Gen3, and QPI applications. The part supports Spread Spectrum
and synthesizes several additional output frequencies from either
a 14.31818 MHz crystal, a 25 MHz crystal or reference input clock.
The 9FG830 also outputs a copy of the reference clock. Complete
control of the device is available via strapping pins or via the
SMBus interface.
9FG830
Features/Benefits:
•
•
•
•
•
Pin-to-Pin with 9FG108D; Easy upgrade to PCIe Gen3
Generates common frequencies from 14.318 MHz or 25
MHz; single part supports mulitple applications
Provides copy of reference output; eleminates need for
additional crystal or oscillator
Three spread spectrum modes: -0.5%, +/-0.25%, and off;
EMI reduction
Unused outputs may be disabled in Hi-Z; save system
power
Device may be configured by SMBus and/or strap pins;
can be used in systems without SMBus
Recommended Application:
8 Output Differential Output Frequency Generator for PCIe Gen3
and QPI
•
Output Features:
•
•
8 - 0.7V current mode differential HCSL output pairs
1 - 3.3V LVTTL REF output
Key Specifications:
•
•
•
•
•
Cycle-to-cycle jitter: < 50ps with 25MHz input
Output-to-output skew: <50ps
Phase jitter: PCIe Gen3 < 1ps rms
Phase jitter: QPI 9.6GB/s < 0.2ps rms
10 ppm synthesis error with 25MHz input and Spread Off
Functional Block Diagram
XIN/CLKIN
X2
OE(7:0)
OSC
REFOUT
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
8
DIF(7:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
IDT
®
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680E—04/04/17
1
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Pin Configuration
XIN/CLKIN
X2
VDD
GND
REFOUT
vFS2
vOE_7
DIF_7
DIF_7#
VDD
DIF_6
DIF_6#
^OE_6
VDD
GND
^OE_5
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
vOE_4
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
vFS0
vFS1
vOE_0
DIF_0
DIF_0#
VDD
DIF_1
DIF_1#
^OE_1
VDD
GND
^OE_2
DIF_2
DIF_2#
VDD
DIF_3
DIF_3#
vOE_3
^SEL14M_25M#
vSPREAD
DIF_STOP#
^ indicates internal 120K pull up
v indicates internal 120K pull down
9FG830
Power Groups
Pin Number
VDD
GND
3
4
10,14,19,31,36,40
15,35
N/A
47
48
47
Description
REFOUT, Digital Inputs, SMBus
DIF Outputs
IREF
Analog VDD & GND for PLL Core
Frequency Select Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
100.00
0
0
0
1
125.00
0
0
1
0
133.33
0
0
1
1
166.67
0
1
0
0
200.00
0
1
0
1
266.67
0
1
1
0
333.33
0
1
1
1
400.00
1
0
0
0
100.00
1
0
0
1
125.00
1
0
1
0
133.33
1
0
1
1
166.67
1
1
0
0
200.00
1
1
0
1
266.67
1
1
1
0
333.33
1
1
1
1
400.00
1680E—04/04/17
IDT
®
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
2
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
PIN NAME
XIN/CLKIN
X2
VDD
GND
REFOUT
vFS2
vOE_7
DIF_7
DIF_7#
VDD
DIF_6
DIF_6#
^OE_6
VDD
GND
^OE_5
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
vOE_4
SDATA
SCLK
DIF_STOP#
vSPREAD
^SEL14M_25M#
PIN TYPE
IN
OUT
PWR
PWR
OUT
IN
IN
OUT
OUT
PWR
OUT
OUT
IN
PWR
PWR
IN
OUT
OUT
PWR
OUT
OUT
IN
I/O
IN
IN
IN
IN
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
Frequency select pin. This pin has an internal 120k pull down resistor
Active high input for enabling output 7. This pin has a 120kohm pull down.
0 =disable outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 6. This pin has an internal 120kohm pull up.
0 = disable outputs, 1= enable outputs
Power supply, nominal 3.3V
Ground pin.
Active high input for enabling output 5. This pin has an internal 120kohm pull up.
0 = disable outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 4. This pin as an internal 120kohm pull down.
0 =disable outputs, 1= enable outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum functionality. This pin has
a 120Kohm pull down resistor.
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
1 = 14.31818 MHz, 0 = 25 MHz
Active high input for enabling output 3. This pin has an internal 120kohm pull down
resistor.
0 =disable outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
28
29
30
vOE_3
DIF_3#
DIF_3
IN
OUT
OUT
IDT
®
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680E—04/04/17
3
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Pin Description (Continued)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Note:
VDD
DIF_2#
DIF_2
^OE_2
GND
VDD
^OE_1
DIF_1#
DIF_1
VDD
DIF_0#
DIF_0
vOE_0
vFS1
vFS0
IREF
GNDA
VDDA
PWR
OUT
OUT
IN
PWR
PWR
IN
OUT
OUT
PWR
OUT
OUT
IN
IN
IN
OUT
PWR
PWR
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 2. This pin has in internal 120kohm pull up
resistor.
0 = disable outputs, 1= enable outputs
Ground pin.
Power supply, nominal 3.3V
Active high input for enabling output 1. This pin has an internal 120kohm pull up
resistor.
0 = disable outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 0. This pin has an internal 120kohm pull down
resistor.
0 =disable outputs, 1= enable outputs
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
^ indicates internal 120K pull up
v indicates internal 120K pull down
IDT
®
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680E—04/04/17
4
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDA
VDD
V
IL
V
IH
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
MIN
TYP
MAX
4.6
4.6
V
DD
+0.5V
5.5V
UNITS NOTES
V
V
V
V
V
°
GND-0.5
Except for SMBus interface
SMBus clock and data pins
-65
Human Body Model
2000
150
125
C
°C
V
1,2
1,2
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
SYMBOL
T
COM
T
IND
V
IH
V
IL
I
IN
Input Current
I
INP
CONDITIONS
Commmercial range
Industrial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, V
IN
= GND, V
IN
= VDD
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
SEL14M_25M# = 0
SEL14M_25M# = 1
Logic Inputs
Crystal inputs
Output pin capacitance
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
DIF_STOP# de-assertion
Fall time of control inputs
Rise time of control inputs
1.5
MIN
0
-40
2
GND - 0.3
-5
TYP
MAX
70
85
V
DD
+ 0.3
0.8
5
UNITS NOTES
°C
°C
V
V
uA
1
1
1
1
1
-200
200
uA
1
Input Frequency
Pin Inductance
Capacitance
F
in
L
pin
C
IN
C
INXTAL
C
OUT
T
STAB
f
MODIN
t
LATOE#
t
DRVDS
t
F
t
R
V
ILSMB
V
IHSMB
V
OLSMB
I
PULLUP
V
DDSMB
t
RSMB
t
FSMB
f
MAXSMB
25
14.31818
7
5
6
6
2.5
30
1
33
3
300
5
5
0.8
2.1
V
DDSMB
0.4
5.5
1000
300
100
MHz
MHz
nH
pF
pF
pF
ms
kHz
cycles
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1
1
1
1
1
1
1,2
1
1,3
1,3
1,2
1,2
1
1
1
1
1
1
1
1
Clk Stabilization
SS Modulation Frequency
OE# Latency
Tdrive_STOP#
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
1
2
@ I
PULLUP
@ V
OL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
4
2.7
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
IDT
®
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680E—04/04/17
5
