4-Output 3.3V PCIe Clock
Generator
9FGL0441 / 9FGL0451
Datasheet
Description
The 9FGL0441 / 9FGL0451 devices are 4-output clock generators
in IDT's 3.3V Full-Featured PCIe family. Each output has a
dedicated OE# pin for clock management. Two different spread
spectrum levels in addition to spread off are supported. The
9FGL0441 / 9FGL0451 supports PCIe Gen1–4 Common Clocked
architectures (CC) and PCIe Separate Reference no-Spread
(SRnS) and Separate Reference Independent Spread (SRIS)
clocking architectures.
Features
▪
Direct connection to loads saves 16 resistors compared to
standard PCIe devices
▪
142mW typical power consumption
▪
SMBus-selectable optimization features:
Typical Applications
▪
Servers/High-Performance Computing/Accelerators
▪
Storage
▪
Embedded Systems/Industrial Control
33Ω, 85Ω or 100Ω output impedance for each output
▪
SMBus interface not required for device operation at default
configuration
▪
Contact factory for customized versions
•
•
•
•
•
Control input polarity
Control input pull-up/pull-down
Slew rate for each output
Differential output amplitude
Output Features
▪
Four 100MHz Low-Power HCSL (LP-HCSL) DIF pairs:
▪
25MHz input frequency
▪
4 OE# pins
▪
Pin-selectable SRnS, CC 0% and CC/SRIS -0.5% spread on
DIF outputs
•
9FGL0441 default Zo = 100Ω
•
9FGL0451 default Zo = 85Ω
▪
One 3.3V LVCMOS REF output; Wake-On-LAN (WOL) support
▪
See
AN-891
for easy AC-coupling to other logic families
▪
SMBus-selectable CC/SRIS -0.25% spread
▪
Clean switching between the CC/SRIS spread spectrum
amounts
▪
DIF outputs blocked until PLL is locked; clean system start-up
Key Specifications
▪
▪
▪
▪
▪
▪
PCIe Gen1–4 CC compliant; Gen2–3 SRIS compliant
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF 12kHz–20MHz phase jitter is < 2ps rms when SSC is off
REF phase jitter < 300fs rms; SSC off and < 1.5ps rms; SSC on
±100ppm frequency accuracy on all clocks
▪
2 selectable SMBus addresses
▪
Space-saving 5 × 5 mm 32-VFQFPN package
Block Diagram
VDDA
vOE(3:0)#
XIN/CLKIN_25
25MHz
X2
vSADR
^vSS_EN_tri
SDATA_3.3
SCLK_3.3
^CKPWRGD_PD#
SSC Capable
PLL
4
REF
VDDREF, VDDXTAL
VDDDIG
VDDO x2
DIF3#
DIF3
DIF2#
DIF2
DIF1#
DIF1
DIF0#
DIF0
Control
Logic
GNDA
GNDDIG
GND x3
EPAD/GND GNDXTAL, GNDREF
©2018 Integrated Device Technology, Inc.
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9FGL0441 / 9FGL0451 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Alternate Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
©2018 Integrated Device Technology, Inc.
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September 18, 2018
9FGL0441 / 9FGL0451 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 5 × 5 mm 32-VFQFPN Package – Top View
^CKPWRGD_PD#
^vSS_EN_tri
32 31 30 29 28 27 26 25
GNDXTAL 1
XIN/CLKIN_25 2
X2 3
VDDXTAL3.3 4
VDDREF3.3 5
vSADR/REF3.3 6
GNDREF 7
GNDDIG 8
9 10 11 12 13 14 15 16
VDDDIG3.3
SDATA_3.3
SCLK_3.3
VDDO3.3
DIF0
vOE0#
DIF0#
GND
24 vOE2#
23 DIF2#
VDDO3.3
22 DIF2
21 VDDA3.3
20 GNDA
19 DIF1#
18 DIF1
17 vOE1#
vOE3#
DIF3#
DIF3
GND
9FGL0441
9FGL0451
EPAD is GND
32-VFQFPN, 5 x 5 mm, 0.5mm pitch
v
^
^v
prefix indicates internal 120kOhm pull-down resistor
prefix indicates internal 120kOhm pull-up resistor
prefix indicates internal 120kOhm pull-up and pull-down resistors
Pin Descriptions
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
Name
GNDXTAL
XIN/CLKIN_25
X2
VDDXTAL3.3
VDDREF3.3
vSADR/REF3.3
GNDREF
GNDDIG
VDDDIG3.3
SCLK_3.3
SDATA_3.3
Type
GND
Input
Output
Power
Power
Latched I/O
GND
GND
Power
Input
I/O
Ground for crystal.
GND
Description
Crystal input or reference clock input. Nominally 25MHz.
Crystal output.
Power supply for XTAL. Nominally 3.3V
Power supply for REF output. Nominally 3.3V.
Latch to select SMBus address/3.3V LVCMOS copy of X1/REFIN pin.
Ground pin for the REF outputs.
Ground pin for digital circuitry.
3.3V digital power (dirty power).
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
©2018 Integrated Device Technology, Inc.
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September 18, 2018
9FGL0441 / 9FGL0451 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
12
13
14
15
16
17
18
19
20
21
22
23
24
52
26
27
28
29
30
31
32
33
Name
vOE0#
DIF0
DIF0#
GND
VDDO3.3
vOE1#
DIF1
DIF1#
GNDA
VDDA3.3
DIF2
DIF2#
vOE2#
VDDO3.3
GND
DIF3
DIF3#
vOE3#
GND
^CKPWRGD_PD#
^vSS_EN_tri
EPAD
Type
Input
Output
Output
GND
Power
Input
Output
Output
GND
Power
Output
Output
Input
Power
GND
Output
Output
Input
GND
Input
Latched In
GND
Description
Active low input for enabling output 0. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
Differential true clock output.
Differential complementary clock output.
Ground pin.
Power supply for outputs. Nominally 3.3V.
Active low input for enabling output 1. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
Differential true clock output.
Differential complementary clock output.
Ground pin for the PLL core.
3.3V power for the PLL core.
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 2. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
Power supply for outputs. Nominally 3.3V.
Ground pin.
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 3. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion. Low
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal pull-up resistor.
Latched select input to select spread spectrum amount at initial power-up. See
Spread
Selection
table.
Connect to ground.
©2018 Integrated Device Technology, Inc.
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September 18, 2018
9FGL0441 / 9FGL0451 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 9FGL0441 / 9FGL0451 at absolute maximum ratings is not implied. Exposure to absolute maximum
rating conditions may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD Protection
1
Guaranteed
2
3
Symbol
V
DDx
V
IN
V
IHSMB
Ts
Tj
ESD prot
Conditions
Minimum
-0.5
-0.5
Maximum
4.6
V
DD
+ 0.5
3.9
150
125
Units
V
V
V
°C
°C
V
Notes
1,2
1,3
1
1
1
1
SMBus clock and data pins.
-65
Human Body Model.
2500
by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
Not to exceed 4.6V.
Thermal Characteristics
Table 3. Thermal Characteristics
Symbol
θ
JC
θ
Jb
θ
JA0
θ
JA1
θ
JA3
θ
JA5
1
EPAD
Parameter
Junction to case.
Junction to base.
Junction to air, still air.
Junction to air, 1 m/s air flow.
Junction to air, 3 m/s air flow.
Junction to air, 5 m/s air flow.
Package
Typical Values
42
2.4
39
33
28
27
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1
1
1
1
1
1
NLG32
soldered to board.
Electrical Characteristics
T
A
= T
AMB
. Supply voltages per normal operation conditions; see
Test Loads
for loading conditions.
Table 4. SMBus Parameters
Parameter
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Symbol
V
ILSMB
V
IHSMB
V
OLSMB
I
PULLUP
Conditions
V
DDSMB
= 3.3V.
V
DDSMB
= 3.3V.
At I
PULLUP.
At V
OL.
Minimum
Typical
Maximum
0.8
Units
V
V
V
mA
Notes
2.1
4
3.6
0.4
©2018 Integrated Device Technology, Inc.
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