DATASHEET
56-pin CK505 for Intel Systems
Recommended Application:
56-pin CK505 compatible clock, w/fully integrated Vreg and series
resistors on differential outputs
Output Features:
•
2 - CPU differential low power push-pull pairs
•
7 - SRC differential push-pull pairs
•
1 - CPU/SRC selectable differential low power push-pull pair
•
1 - SRC/DOT selectable differential low power push-pull pair
•
1 - SRC/SE selectable differential push-pull pair/Single-ended
outputs
•
5 - PCI, 33MHz
•
1 - USB, 48MHz
•
1 - REF, 14.318MHz
Key Specifications:
•
CPU outputs cycle-cycle jitter <85ps
•
SRC output cycle-cycle jitter <85ps
•
PCI outputs cycle-cycle jitter <250ps
•
+/- 100ppm frequency accuracy on all outputs
•
SRC outputs meet PCIe Gen2 when sourced from PLL3
Pin Configuration
PCI0/CR#_A 1
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3/CFG0
PCI4/SRC5_EN
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96IO
DOTT_96_LRS/SRCT0_LRS
DOTC_96_LRS/SRCC0_LRS
GND
VDD
SRCT1_LRS/SE1
SRCC1_LRS/SE2
GND
VDDPLL3IO
SRCT2_LRS/SATAT_LRS
SRCC2_LRS/SATAC_LRS
GNDSRC
SRCT3_LRS/CR#_C
SRCC3_LRS/CR#_D
VDDSRCIO
SRCT4_LRS
SRCC4_LRS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 SCLK
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SDATA
REF0/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT0_LRS
CPUC0_LRS
GNDCPU
CPUT1_F_LRS
CPUC1_F_LRS
VDDCPUIO
NC
CPUT2_ITP_LRS/SRCT8_LRS
CPUC2_ITP_LRS/SRCC8_LRS
VDDSRCIO
SRCT7_LRS/CR#_F
SRCC7_LRS/CR#_E
GNDSRC
SRCT6_LRS
SRCC6_LRS
VDDSRC
PCI_STOP#/SRCT5_LRS
CPU_STOP#/SRCC5_LRS
ICS9LPRS525
Features/Benefits:
•
Supports spread spectrum modulation, 0 to -0.5% down
spread
•
Supports CPU clks up to 400MHz
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Table 1: CPU Frequency Select Table
FS
L
C
B0b7
0
0
0
0
1
1
1
1
2
FS
L
B
B0b6
0
0
1
1
0
0
1
1
1
FS
L
A
B0b5
0
1
0
1
0
1
0
1
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC
MHz
PCI
MHz
REF
MHz
USB DOT
MHz MHz
100.00
33.33 14.318 48.00 96.00
Reserved
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
56-SSOP & TSSOP
IDT
TM
PC MAIN CLOCK
9LPRS525
1484E—07/07/11
1
ICS9LPRS525
PC MAIN CLOCK
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before
configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CRA#_EN bit located in byte 5 of
SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CRA# enabled. Byte 5, bit 6 controls whether CRA# controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CRA# controls SRC0 pair (default),
1= CRA# controls SRC2 pair
Power supply for PCI clocks, nominal 3.3V
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before
configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRB#_EN bit located in byte 5 of
SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CRB# enabled. Byte 5, bit 6 controls whether CRB# controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CRB# controls SRC1 pair (default)
1= CRB# controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable(TME) Latched Input. This pin is sampled on power-up as follows
0=Overclocking of CPU and SRC allowed
1=Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
3.3V PCI clock output/Configuration Strap. See PCI3 Configuration Table for more information
3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is
enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of
this pin determines whether pins 38 and 39 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
Ground pin for the PCI outputs
Power pin for the 48MHz output and PLL.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin for the 48MHz outputs
Power supply for DOT96 outputs, 1.05V to 3.3V.
True clock of low power differential SRC or DOT96 with integrated 33 ohm Rs. The power-up default function is SRC0. After powerup, this pin function
may be changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
Complement clock of low power differential SRC or DOT96 with integrated 33 ohm Rs. The power-up default function is SRC0#. After powerup, this
pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#
Ground pin.
Power supply, nominal 3.3V
True clock of low power differential SRC1 clock pair with integrated 33 ohm Rs. / 3.3V single-ended output. The powerup default is 100 MHz SRC, -
0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Complement clock of low powerl differential SRC1 clock pair with integrated 33 ohm Rs / 3.3V single-ended output. The powerup default is 100 MHz
SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Ground pin.
Power supply for PLL3 outputs. 1.05V to 3.3V.
True clock of low power differentiall SRC/SATA clock pair with integrated Rs.
Complement clock of low power differential push-pull SRC/SATA clock pair with integrated 33 ohm Rs.
Ground pin for the SRC outputs
True clock of low power differential SRC clock pair with integrated 33 ohm Rs./ Clock Request control C for either SRC0 or SRC2 pair. The power-up
default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this
pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CRC#_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRCCLK3 enabled (default)
1= CRC# enabled. Byte 5, bit 2 controls whether CRC# controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CRC# controls SRC0 pair (default),
1= CRC# controls SRC2 pair
1
PCI0/CR#_A
I/O
2
VDDPCI
PWR
3
PCI1/CR#_B
I/O
4
PCI2/TME
I/O
5
PCI3/CFG0
I/O
6
PCI4/SRC5_EN
I/O
7
PCI_F5/ITP_EN
I/O
8
9
10
11
12
13
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96IO
DOTT_96_LRS/SRCT0_LRS
PWR
PWR
I/O
PWR
PWR
OUT
14
15
16
17
18
19
20
21
22
23
DOTC_96_LRS/SRCC0_LRS
GND
VDD
SRCT1_LRS/SE1
SRCC1_LRS/SE2
GND
VDDPLL3IO
SRCT2_LRS/SATAT_LRS
SRCC2_LRS/SATAC_LRS
GNDSRC
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
24
SRCT3_LRS/CR#_C
I/O
IDT
TM
PC MAIN CLOCK
1484E—07/07/11
2
ICS9LPRS525
PC MAIN CLOCK
Pin Description (continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
Complementary clock of low power differential SRC clock pair with integrated 33 ohm Rs/ Clock Request control D for either SRC1 or SRC4 pair.
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before
configuring this pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is
disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRD#_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CRD# enabled. Byte 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CRD# controls SRC1 pair (default),
1= CRD# controls SRC4 pair
Power supply for SRC outputs. 1.05V to 3.3V.
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.
Stops all CPUCLK, except those set to be free running clocks /
Complement clock of low power differential SRC pair with 33 ohm integrated Rs.
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. / True clock of low power differential SRC pair
with integrated 33 ohm Rs.
Supply for SRC PLL, 3.3V nominal
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.
Ground pin for the SRC outputs
Complement clock of differential push-pull SRC clock pair with 33 ohm integrated Rs. / Clock Request control E for SRC6 pair. The power-up default
is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CRE# enabled.
True clock of differential push-pull SRC clock pair/ Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock
Request Pin, the SR
Power supply for SRC outputs. 1.05V to 3.3V.
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is determined by the
latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
25
SRCC3_LRS/CR#_D
I/O
26
27
28
29
30
31
32
33
34
VDDSRCIO
SRCT4_LRS
SRCC4_LRS
CPU_STOP#/SRCC5_LRS
PCI_STOP#/SRCT5_LRS
VDDSRC
SRCC6_LRS
SRCT6_LRS
GNDSRC
PWR
OUT
OUT
I/O
I/O
PWR
OUT
OUT
PWR
35
SRCC7_LRS/CR#_E
I/O
36
37
SRCT7_LRS/CR#_F
VDDSRCIO
I/O
PWR
38
CPUC2_ITP_LRS/SRCC8_LRS
OUT
39
CPUT2_ITP_LRS/SRCT8_LRS
OUT
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
VDDCPUIO
CPUC1_F_LRS
CPUT1_F_LRS
GNDCPU
CPUC0_LRS
CPUT0_LRS
VDDCPU
CK_PWRGD/PD#
FSLB/TEST_MODE
GNDREF
X2
X1
VDDREF
REF0/FSLC/TEST_SEL
SDATA
SCLK
N/A
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
PWR
OUT
IN
PWR
I/O
I/O
IN
No Connect
Power supply for CPU outputs, 1.05V to 3.3V.
Complementary clock of low power differential push-pull CPU output with integrated 33 ohm Rs. This CPU clock is free running during iAMT.
True clock of differential push-pull CPU clock pair with integrated 33 ohm Rs. This clock is free running during iAMT.
Ground pin for the CPU outputs
Complement clock of low power differential CPU clock pair with integrated 33 ohm Rs.
True clock of low power differential CPU clock pair with integrated 33 ohm Rs.
Supply for CPU PLL, 3.3V nominal
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.
Ground pin for the REF outputs.
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
/TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
IDT
TM
PC MAIN CLOCK
1484E—07/07/11
3
ICS9LPRS525
PC MAIN CLOCK
General Description
ICS9LPRS525
is compliant Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop
chipsets.
ICS9LPRS525
is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express
support.
Block Diagram
X1
X2
REF
REF
CPU(1:0)
OSC
SRC8/ITP
CPU
CPU PLL1
SS
SRC
SRC_MAIN
SRC(7:3)
PCI33MHz
SRC
PCI(5:0)
PCI33MHz
PLL3
SS
SRC2/SATA
FSLA
CKPWRGD/PD#
PCI_STOP#
CPU_STOP#
CR#_(A:F)
SRC5_EN
ITP_EN
FSLC/TESTSEL
FSLB/TESTMODE
SRC1/SE(2:1)
Control
Logic
Differential Output
SE Outputs
7
SATA
SRC0/DOT96
PLL2
Non-SS
DOT96MHz
48MHz
48MHz
Power Groups
Pin Number
VDD
GND
41, 47
44
16
15
26, 31, 37
20
12
9
53
2
IDT
TM
PC MAIN CLOCK
Description
CPUCLK
Master Clock, Analog
SRCCLK
PLL3/SE
DOT 96Mhz
USB 48
Xtal, REF
PCICLK
1484E—07/07/11
23, 34
19
11
11
50
8
4
ICS9LPRS525
PC MAIN CLOCK
Absolute Maximum Ratings - DC Parameters
PARAMETER
Maximum Supply Voltage
Maximum Supply Voltage
Maximum Input Voltage
Minimum Input Voltage
Storage Temperature
Case Temperature
Input ESD protection
1
2
3
SYMBOL
VDDxxx
VDDxxx_IO
V
IH
V
IL
Ts
Tc
ESD prot
CONDITIONS
Supply Voltage
Low-Voltage Differential I/O Supply
3.3V Inputs
Any Input
-
Human Body Model
MIN
MAX
4.6
3.8
4.6
150
115
GND - 0.5
-65
2000
UNITS Notes
V
7
V
7
V
4,5,7
V
4,7
°
4,7
C
°
4,7
C
V
6,7
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied, nor guaranteed.
Maximum input voltage is not to exceed VDD
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER
Ambient Operating Temp
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Low Threshold Input- High Voltage
Low Threshold Input- FSC = '1' Voltage
Low Threshold Input- FSA,FSB = '1'
Voltage
Low Threshold Input-Low Voltage
PCI3/CFG0 Input
PCI3/CFG0 Input
PCI3/CFG0 Input
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
iAMT Mode Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
SYMBOL
Tambient
VDDxxx
VDDxxx_IO
V
IHSE
V
IL SE
V
IH _FS_ TEST
V
IH _FS_ FSC
V
IH_F S_F SAB
V
IL _FS
V
I L_CF GHI
V
IL _CF GMID
V
IL_ CF GLO
I
IN
I
INR ES
V
OHSE
V
OLSE
I
D DOP3.3
I
D DOPIO
I
DD iAM T3.3
I
D DiAMTIO
I
D DPD 3.3
I
DDPD IO
F
i
L
pin
C
IN
C
OUT
C
IN X
T
ST AB
T
DR CROF F
T
DRC RON
T
DR SRC
T
F ALL
T
R ISE
V
DD
V
OLSM B
I
PULLU P
T
RI2C
T
F I2C
F
SMBU S
f
SSM OD
Triangular Modulation
30
CONDITIONS
-
Supply Voltage
Low-Voltage Differential I/O Supply
Single-ended 3.3V inputs
Single-ended 3.3V inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
Optional input, 2.75V typ.
Optional input, 1.65V typ.
Optional input, 0.55V typ.
V
IN
= V
DD ,
V
IN
= GND
Inputs with pull up or pull down resistors
V
IN
= V
DD ,
V
IN
= GND
Single-ended outputs, I
OH
= -1mA
Single-ended outputs, I
OL
= 1 mA
Full Active, C
L
= Full load; Idd 3.3V
Full Active, C
L
= Full load; IDD IO
M1 mode, 3.3V Rail
M1 Mode, IO Rail
Power down mode, 3.3V Rail
Power down mode, IO Rail
V
DD
= 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-assertion of PD to 1st
clock
Output stop after CR deasserted
Output run after CR asserted
CPU output enable after
PCI_STOP# de-assertion
Fall/rise time of all 3.3V control inputs from 20-80%
2.7
@ I
PU LLU P
SMB D ata Pin
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
4
1000
300
100
33
MIN
0
3.135
0.9975
2
V
SS
- 0.3
2
0.7
0.7
V
SS
- 0.3
2.4
1.3
V
SS
- 0.3
-5
-200
2.4
0.4
150
70
40
12
6
0.7
15
7
5
6
6
1.8
400
0
10
10
10
5.5
0.4
MAX
U NITS Notes
70
°C
3.465
V
3.465
V
10
V
D D
+ 0.3
V
3
0.8
V
3
VDD + 0.3
V
8
1.5
VDD+0.3
0.35
VDD+0.3
2
0.9
5
200
V
V
V
V
V
V
uA
uA
V
V
mA
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
ms
ns
us
ns
ns
ns
V
V
mA
ns
ns
kHz
kHz
1
1
10
9, 10
9, 10
9, 10
2
8
10
1.5
Clk Stabilization
Tdrive_CR_off
Tdrive_CR_on
Tdrive_CPU
Tfall_SE
Trise_SE
SMBus Voltage
Low-level Output Voltage
Current sinking at V
OL SMB
= 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
Maximum SMBus Operating Frequency
Spread Spectrum Modulation Frequency
IDT
TM
PC MAIN CLOCK
1484E—07/07/11
5
