DATASHEET
64-pin CK505 Compatible Clock w/Fully Integrated Voltage
Regulator + Integrated Series Resistor
Recommended Application:
CK505 compatible clock with fully integrated voltage regulator and
Internal series resistor on differential outputs
Output Features:
•
2 - CPU differential low power push-pull pairs
•
9 - SRC differential low power push-pull pairs
•
1 - CPU/SRC selectable differential low power push-pull pair
•
1 - SRC/DOT selectable differential low power push-pull pair
•
5 - PCI, 33MHz
•
1 - PCI_F, 33MHz free running
•
1 - USB, 48MHz
•
1 - REF, 14.318MHz
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 250ps
•
+/- 100ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
•
Does not require external pass transistor for voltage regulator
•
Integrated 33ohm series resistors on differential outputs,
Z
o
=50Ω
• Supports spread spectrum modulation, default is 0.5% down
spread
•
Uses external 14.318MHz crystal, external crystal load caps
are required for frequency tuning
•
•
Selectable between one SRC differential push-pull pair and
two single-ended outputs
Meets PCIEX Gen2 specification on dedicated SRC outputs.
Muxed SRC outputs meet PCIEX Gen1 specification, except
SRC1.
Single-ended programmable slew rate control for RFI
reduction
Meets PCIEX <85ps cycle-to-cycle jitter for SRC[11:1]
Table 1: CPU Frequency Select Table
9LRS3165B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT_LR0
CPUC_LR0
GNDCPU
CPUT_F_LR1
CPUC_F_LR1
VDDCPU_IO
NC
CPUT_ITP_LR2/SRCT8
CPUC_ITP_LR2/SRCC8
VDDSRCI/O
SRCT_LR7/CR#_F
SRCC_LR7/CR#_E
GNDSRC
SRCT_LR6
SRCC_LR6
VDDSRC
PCI_STOP#
CPU_STOP#
VDDSRCI/O
SRCC_LR10
SRCT_LR10
SRCT_LR11/CR#_H
Pin Configuration
PCI0/CR#_A
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SEL
PCI5_F/ITP_EN
GNDPCI
VDD48
USB48M/FSLA
GND48
VDDI/O96MHz
DOT96T/SRCT_LR0
DOT96C/SRCC_LR0
GND
VDD
27FIX/LCDT/SRCT_LR1/SE1
27SS/LCDC/SRCC_LR1/SE2
GND
VDDPLL3I/O
SRCT_LR2/SATACLKT
SRCC_LR2/SATACLKC
GNDSRC
SRCT_LR3/CR#_C
SRCC_LR3/CR#_D
VDDSRCI/O
SRCT_LR4
SRCC_LR4
GNDSRC
SRCT_LR9
SRCC_LR9
SRCC_LR11/CR#_G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64-TSSOP
•
•
2
1
1
CPU
SRC
PCI
REF
USB
DOT
FS
L
C
FS
L
B
FS
L
A
MHz
MHz
MHz
MHz
MHz
MHz
B0b7
B0b6
B0b5
0
0
0
266.66
0
0
1
133.33
0
1
0
200.00
0
1
1
166.66
48.00
100.00
33.33 14.318
96.00
1
0
0
333.33
1
0
1
100.00
1
1
0
400.00
1
1
1
Reserved
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
ICS9LRS3165B
1533B—01/06/15
1
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
TSSOP Pin Description
Pin# Pin Name
Type DESCRIPTION
1
PCI0/CR#_A
I/O
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock
Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this
pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0
of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using
the CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled.
Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
2
VDDPCI
PWR Power supply pin for the PCI outputs, 3.3V nominal
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock
Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this
pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1
of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using
the CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled.
Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
3
PCI1/CR#_B
I/O
4
PCI2/TME
5
6
PCI3
PCI4/27_SEL
7
PCI5_F/ITP_EN
8
9
10
11
12
13
14
15
16
GNDPCI
VDD48
USB48M/FSLA
GND48
VDDI/O96MHz
DOT96T/SRCT_LR0
DOT96C/SRCC_LR0
GND
VDD
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is
sampled on power-up as follows
I/O 0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
OUT 3.3V PCI clock output.
3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the
I/O logic value on this pin determines the power-up default of DOT_96/SRC0 and
27MHz/SRC1 output and the function table for the pin17 and pin18.
Free running PCI clock output and ITP/SRC8 enable strap. This output is not
affected by the state of the PCI_STOP# pin. On powerup, the state of this pin
I/O determines whether pins 46 and 47 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
PWR Ground for PCI clocks.
PWR Power supply for USB clock, nominal 3.3V.
I/O
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
PWR Ground pin for the 48MHz outputs.
PWR 1.05V to 3.3V from external power supply
True clock of SRC or DOT96. The power-up default function depends on
OUT
27_Select,1= SRC0, 0=DOT96
Complement clock of SRC or DOT96. The power-up default function depends
OUT
on 27_Select,1= SRC0, 0=DOT96
PWR Ground pin for the DOT96 clocks.
PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1533B—01/06/15
2
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
TSSOP Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
Single-ended 3.3V 27MHz fix clock output / True clock of differential SRC1 or LCD
clock pair / Single ended 3.3V peripheral clock output. The default output selection
is determined by the SEL_27 default latch value. See below:
OUT
27_SEL=0:
LCD100 with -0.5% down spread is selected as default. LCD100 spread
percentage can be adjusted OR output can be changed to SRC or 3.3V single-ended
peripheral clock output via SMBUs B1b[4:1].
27_SEL=1:
Single-ended 27FIX output is selected.
Single-ended 3.3V 27MHz fix clock output / Complementary clock of differential
SRC1 or LCD clock pair / Single ended 3.3V peripheral clock output. The default
output selection is determined by the SEL_27 default latch value. See below:
27_SEL=0:
LCD100 with -0.5% down spread is selected as default. LCD100 spread
OUT
percentage can be adjusted OR output can be changed to SRC or 3.3V single-ended
peripheral clock output via SMBUs B1b[4:1].
27_SEL=1:
Single-ended 27SS output is selected with -0.5% down spread as
default. Spread percentage can be adjusted via SMBus B1b[4:1].
PWR
PWR
OUT
OUT
PWR
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
1.05V to 3.3V from external power supply
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or
SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock
Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin
as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of
SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled.
Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
Complementary clock of differential SRC clock pair/ Clock Request control D for
either SRC1 or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock
Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin
as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of
SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled.
Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
1.05V to 3.3V from external power supply
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request
control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration
space After the SRC11 output is disabled (high-Z), the pin can then be set to serve
as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
17
27FIX/LCDT/SRCT_LR1/SE1
18
27SS/LCDC/SRCC_LR1/SE2
19
20
21
22
23
GND
VDDPLL3I/O
SRCT_LR2/SATACLKT
SRCC_LR2/SATACLKC
GNDSRC
24
SRCT_LR3/CR#_C
I/O
25
SRCC_LR3/CR#_D
I/O
26
27
28
29
30
31
VDDSRCI/O
SRCT_LR4
SRCC_LR4
GNDSRC
SRCT_LR9
SRCC_LR9
PWR
I/O
I/O
PWR
OUT
OUT
32
SRCC_LR11/CR#_G
I/O
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1533B—01/06/15
3
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
TSSOP Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request
control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration
space After the SRC11 output is disabled (high-Z), the pin can then be set to serve
as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
33
SRCT_LR11/CR#_H
I/O
34
35
36
37
38
39
40
41
42
SRCT_LR10
SRCC_LR10
VDDSRCI/O
CPU_STOP#
PCI_STOP#
VDDSRC
SRCC_LR6
SRCT_LR6
GNDSRC
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR 1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3
IN
bits are shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits
IN
are shifted in from the ICH to set the FSC, FSB, FSA values
PWR VDD pin for SRC Pre-drivers, 3.3V nominal
OUT Complement clock of low power differential SRC clock pair.
OUT True clock of low power differential SRC clock pair.
PWR Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request
control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
. After the SRC output is disabled (high-Z), the pin can then be set to serve as a
Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request
control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock
Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential
SRC pair. The function of this pin is determined by the latched input value on pin 7,
PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The
function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN
on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
1.05V to 3.3V from external power supply
Complement clock of low power differenatial CPU clock pair. This clock will be free-
running during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running
during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
43
SRCC_LR7/CR#_E
I/O
44
SRCT_LR7/CR#_F
I/O
45
VDDSRCI/O
PWR
46
CPUC_ITP_LR2/SRCC8
OUT
47
CPUT_ITP_LR2/SRCT8
OUT
48
49
50
51
52
53
54
55
56
NC
VDDCPU_IO
CPUC_F_LR1
CPUT_F_LR1
GNDCPU
CPUC_LR0
CPUT_LR0
VDDCPU
CK_PWRGD/PD#
N/A
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
57
58
59
60
61
62
63
64
FSLB/TEST_MODE
GNDREF
X2
X1
VDDREF
REF/FSLC/TEST_SEL
SDATA
SCLK
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to
IN
select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
PWR Ground pin for crystal oscillator circuit
OUT Crystal output, nominally 14.318MHz.
IN Crystal input, Nominally 14.318MHz.
PWR Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/
I/O
TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification
Table.
I/O Data pin for SMBus circuitry, 5V tolerant.
IN Clock pin of SMBus circuitry, 5V tolerant.
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1533B—01/06/15
4
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
Pin Configuration
CPUC_ITP_LR2/SRCC8
CPUT_ITP_LR2/SRCT8
FSLB/TEST_MODE
SRCC_LR7/CR#_E
SRCT_LR7/CR#_F
CK_PWRGD/PD#
CPUC_F_LR1
CPUT_F_LR1
VDDCPU_IO
VDDSRCI/O
CPUC_LR0
CPUT_LR0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GNDREF
X2
X1
VDDREF
REF/FSLC/TEST_SEL
SDATA
SCLK
PCI0/CR#_A
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SEL
PCI5_F/ITP_EN
GNDPCI
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND48
DOT96T/SRCT_LR0
USB48M/FSLA
VDDI/096MHz
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SRCC_LR2/SATACLKC
GNDSRC
SRCT_LR3/CR#_C
SRCC_LR3/CR#_D
SRCT_LR6
SRCC_LR6
VDDSRC
PCI_STOP#
CPU_STOP#
VDDSRC_IO
SRCC_LR10
SRCT_LR10
SRCT_LR11/CR#_H
SRCC_LR11/CR#_G
SRCC_LR9
SRCT_LR9
GNDSRC
SRCC_LR4
SRCT_LR4
VDDSRCI/O
ICS9LRS3165B
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
27FIX/LCDT/SRCT_LR1/SE1
27SS/LCDC/SRCC_LR1/SE2
DOT96C/SRCC_LR0
GND
VDD
VDDPLL3I/O
SRCT_LR2/SATACLKT
64-pin MLF
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
GNDSRC
GNDCPU
VDDCPU
NC
1533B—01/06/15
5
嵌入式系统
